AD9850 Analog Devices, AD9850 Datasheet - Page 3
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AD9850
Manufacturer Part Number
AD9850
Description
CMOS/ 125 MHz Complete DDS Synthesizer
Manufacturer
Analog Devices
Datasheet
1.AD9850.pdf
(19 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9850
Manufacturer:
TI/德州仪器
Quantity:
20 000
Company:
Part Number:
AD9850BR5
Manufacturer:
ALTERA
Quantity:
1
Company:
Part Number:
AD9850BRS
Manufacturer:
AD
Quantity:
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Part Number:
AD9850BRS
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Parameter
CMOS LOGIC INPUTS (Including CLKIN)
POWER SUPPLY (A
NOTES
*Tested by measuring output duty cycle variation.
Specifications subject to change without notice.
REV. E
TIMING CHARACTERISTICS*
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
NOTES
*Control functions are asynchronous with CLKIN.
Specifications subject to change without notice.
DS
DH
WH
WL
WD
CD
FH
FL
CF
FD
RH
RL
RS
OL
RR
Logic “1” Voltage, +5 V Supply
Logic “1” Voltage, +3.3 V Supply
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
+V
P
P
DISS
DISS
62.5 MHz Clock, +3.3 V Supply
110 MHz Clock, +3.3 V Supply
62.5 MHz Clock, +5 V Supply
125 MHz Clock, +5 V Supply
62.5 MHz Clock, +3.3 V Supply
110 MHz Clock, +3.3 V Supply
62.5 MHz Clock, +5 V Supply
125 MHz Clock, +5 V Supply
+5 V Supply
+3.3 V Supply
(Data Setup Time)
(Data Hold Time)
(W_CLK min. Pulsewidth High)
(W_CLK min. Pulsewidth Low)
(W_CLK Delay After FQ_UD)
(CLKIN Delay After FQ_UD)
(FQ_UD High)
(FQ_UD Low)
(Output Latency from FQ_UD)
Frequency Change
Phase Change
(FQ_UD Min. Delay After W_CLK)
(CLKIN Delay After RESET Rising Edge)
(RESET Falling Edge After CLKIN)
(Minimum RESET Width)
(RESET Output Latency)
(Recovery from RESET)
Wake-Up Time from Power-Down Mode
S
Current @:
@:
Power-Down Mode
OUT
= 1/3 CLKIN)
(V
S
= +5 V
5% except as noted, R
Temp
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
+25°C
–3–
Test Level
I
I
I
I
I
V
VI
VI
VI
VI
VI
VI
VI
VI
V
V
Test Level
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
V
SET
= 3.9 k )
Min
3.5
3.5
3.5
3.5
7.0
3.5
7.0
7.0
18
13
7.0
3.5
3.5
5
13
2
AD9850BRS
Min
3.5
3.0
AD9850BRS
Typ
5
Typ
3
30
47
44
76
100
155
220
380
30
10
Max
Max
0.4
12
12
48
60
64
96
160
200
320
480
Units
ns
ns
ns
ns
ns
ns
ns
ns
CLKIN Cycles
CLKIN Cycles
ns
ns
ns
CLKIN Cycles
CLKIN Cycles
CLKIN Cycles
µs
AD9850
Units
V
V
V
µA
µA
pF
mA
mA
mA
mA
mW
mW
mW
mW
mW
mW