AD9882 Analog Devices, AD9882 Datasheet - Page 20

• Manufacturer Part Number: AD9882
• Description: Dual Interface for Flat Panel Displays
• Manufacturer: Analog Devices

AD9882
POWER SUPPLY
V
PV
V
GND
THEORY OF OPERATION (DIGITAL INTERFACE)
Capturing of the Encoded Data
The first step in recovering the encoded data is to capture the raw
data. To accomplish this, the AD9882 employs a high speed phase
locked loop (PLL) to generate clocks capable of oversampling
the data at the correct frequency. The data capture circuitry
continuously monitors the incoming data during horizontal and
vertical blanking times (when DE is low) and selects the best
sampling phase for each data channel independently. The phase
information is stored and used until the next blanking period
(one video line).
Data Frames
The digital interface data is captured in groups of 10 bits each,
which are called data frames. During the active data period,
each frame is made up of the nine encoded video data bits and
one dc balancing bit. The data capture block receives this
data serially but outputs each frame in parallel 10-bit words.
Special Characters
During periods of horizontal or vertical blanking time (when DE is
low), the digital transmitter will transmit special characters. The
AD9882 will receive these characters and use them to set the video
frame boundaries and the phase recovery loop for each chan-
nel. There are four special characters that can be received.
They are used to identify the top, bottom, left side, and right
side of each video frame. The data receiver can differentiate
these special characters from active data because the special
characters have a different number of transitions per data frame.
Channel Resynchronization
The purpose of the channel resynchronization block is to
resynchronize the three data channels to a single internal data
clock. Coming into this block, all three data channels can be on
different phases of the 3¥ oversampling PLL clock (0∞, 120∞,
and 240∞). This block can resynchronize the channels from a
worst-case skew of one full input period (8.93 ns at 112 MHz).
D
DD
D
Main Power Supply
It should be as quiet as possible.
PLL Power Supply
It should be as quiet as possible.
Outputs Power Supply
The power for the data and clock outputs. It can
run at 3.3 V or 2.5 V.
Ground
The ground return for all circuitry on the device.
It is recommended that the application circuit
board have a single, solid ground plane.
DVI
CONNECTOR
DDC CLOCK
DDC DATA
Figure 10. HDCP Implementation Using the AD9882
D
S
3.3V
3.3V
150
RESISTORS
5k
RESISTORS
SERIES
PULL-UP
–20–
DDC SCL
DDC SDA
Data Decoder
The data decoder receives frames of data and sync signals from
the data capture block (in 10-bit parallel words) and decodes
them into groups of eight RGB bits, two control bits, and a data
enable bit (DE).
HDCP
The AD9882 contains all the circuitry necessary for decryption
of a high bandwidth digital content protection encoded DVI
video stream. A typical HDCP implementation is shown in
Figure 10. Several features of the AD9882 make this possible
and add functionality to ease the implementation of HDCP.
The basic components of HDCP are included in the AD9882.
A slave serial bus connects to the DDC clock and DDC data
pins on the DVI connector to allow the HDCP enabled DVI
transmitter to coordinate the HDCP algorithm with the AD9882.
A second serial port (MDA/MCL) allows the AD9882 to read
the HDCP keys and key selection vector (KSV) stored in an
external serial EEPROM. When transmitting encrypted video,
the DVI transmitter enables HDCP through the DDC port.
The AD9882 then decodes the DVI stream using information
provided by the transmitter, HDCP keys, and KSV.
The AD9882 allows the MDA and MCL pins to be three-stated
using the MDA/MCL three-state bit (Register 1B, Bit 7) in the
configuration registers. The three-state feature allows the EEPROM
to be programmed in-circuit. The MDA/MCL port must be
three-stated before attempting to program the EEPROM using
an external master. The keys will be stored in an I
3.3 V serial EEPROM of at least 512 bytes in size. The EEPROM
should have a device address of A0H.
Proprietary software licensed from Analog Devices encrypts
the keys and creates properly formatted EEPROM images for
use in a production environment. Encrypting the keys helps
maintain the confidentiality of the HDCP keys as required by
the HDCP v1.0 specification. The AD9882 includes hard-
ware for decrypting the keys in the external EEPROM.
ADI will provide a royalty free license for the proprietary
software needed by customers to encrypt the keys between
the AD9882 and the EEPROM only after customers provide
evidence of a completed HDCP Adopter’s license agreement
and sign ADI’s software license agreement. The Adopter’s
license agreement is maintained by Digital Content Protection,
LLC, and can be downloaded from www.digital-cp.com.
To obtain ADI’s software license agreement, contact the Display
Electronics Product Line directly by sending an email to
[e-mail].
AD9882
MCL
MDA
3.3V
5k
RESISTORS
SCL
SDA
EEPROM
PULL-UP
2
C compatible
REV. A