AD9889B Analog Devices, AD9889B Datasheet - Page 7

• Manufacturer Part Number: AD9889B
• Description: High Performance HDMI/DVI Transmitter
• Manufacturer: Analog Devices

Preliminary Technical Data
Table 3. Pin Function Descriptions
BGA
A1 to A10, B1 to
B10, C9, C10,
D9, D10
D1
C2
C1
D2
J3
K3
E2
E1
F2, F1, G2, G1
H2
H1
J7
K1, K2
K10, J10
K7, K8
K4, K5
H10
J2, J5, J8, K9
2
LFCSP
39 to 47,
50 to 63, 2
6
3
4
5
18
20
7
8
9 to 12
13
14
26
21, 22
30, 31
27, 28
24, 25
32
19, 23, 29
Pin No.
2
LQFP
50 to 58, 65 to
78, 2
6
3
4
5
23
25
7
8
9 to 12
13
14
33
27, 28
37, 38
34, 35
30, 31
40
24, 29, 36, 41
2
Figure 4. 76-Ball BGA Configuration (Top View)
Mnemonic
D[23:0]
CLK
DE
HSYNC
VSYNC
EXT_SW
HPD
S/PDIF
MCLK
I
SCLK
LRCLK
PD/A0
TxC−/TxC+
Tx2−/Tx2+
Tx1−/Tx1+
Tx0−/Tx0+
INT
AVDD
2
S[3:0]
10
9
Rev. PrA | Page 7 of 12
BOTTOM VIEW
8 7 6
(Not to Scale)
5 4
Type
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
P
3 2 1
1
Description
Video Data Input. Digital input in RGB or YCbCr format. Supports
CMOS logic levels from 1.8 V to 3.3 V.
Video Clock Input. Supports CMOS logic levels from 1.8 V
to 3.3 V.
Data Enable Bit for Digital Video. Supports CMOS logic levels
from 1.8 V to 3.3 V.
Horizontal Sync Input. Supports CMOS logic levels from 1.8 V
to 3.3 V.
Vertical Sync Input. Supports CMOS logic levels from 1.8 V
to 3.3 V.
Sets internal reference currents. Place 887 Ω resistor (1%
tolerance) between this pin and ground.
Hot Plug Detect Signal. This indicates to the interface
whether the receiver is connected. 1.8 V to 5.0 V CMOS logic
level.
S/PDIF (Sony/Philips Digital Interface) Audio Input. This is the
audio input from a Sony/Philips digital interface. Supports
CMOS logic levels from 1.8 V to 3.3 V.
Audio Reference Clock. 128 × N × f
to 128 × sampling frequency (f
1.8 V to 3.3 V CMOS logic level.
I
audio (two per input) available through I
logic levels from 1.8 V to 3.3 V.
I
Left/Right Channel Selection. Supports CMOS logic levels
from 1.8 V to 3.3 V.
Power-Down Control and I
address and the PD polarity are set by the PD/A0 pin state
when the supplies are applied to the AD9889B. 1.8 V to 3.3 V
CMOS logic level.
Differential Clock Output. Differential clock output at pixel
clock rate; TMDS logic level.
Differential Output Channel 2. Differential output of the red
data at 10× the pixel clock rate; TMDS logic level.
Differential Output Channel 1. Differential output of the
green data at 10× the pixel clock rate; TMDS logic level.
Differential Output Channel 0. Differential output of the blue
data at 10× the pixel clock rate; TMDS logic level.
Interrupt. Open drain. A 2 kΩ pull-up resistor to the
microcontroller I/O supply is recommended.
1.8 V Power Supply for TMDS Outputs.
2
2
S Audio Data Inputs. These represent the eight channels of
S Audio Clock. Supports CMOS logic levels from 1.8 V to 3.3 V.
A
B
C
D
E
F
G
H
J
K
2
C Address Selection. The I
S
), 256 × f
S
with N = 1, 2, 3, or 4. Set
S
2
, 384 × f
S. Supports CMOS
AD9889B
S
, or 512 × f
2
C
S
.