LM2648 National Semiconductor, LM2648 Datasheet - Page 15

• Manufacturer Part Number: LM2648
• Description: Synchronous Step-Down 3-Channel Switching Regulator Controller
• Manufacturer: National Semiconductor

Operation Descriptions
ON and UVLO
The ON/UVLO pin provides a dual threshold shutdown and
under voltage lock out function. When this pin is pulled
above 1.2V, the internal bias circuitry starts up and the
device enters standby mode. The ON/UVLO pin has 149mV
(typical) of hysteresis. This pin also provides a user program-
mable UVLO function. The lock out threshold at this pin is
1.98V with 200mV hysteresis (typical). Above this threshold,
SS1/2 begins to source current. Connecting this pin through
a voltage divider to V
UVLO threshold above the internal UVLO level.
The internal UVLO threshold, which is sensed via the VLIN5
internal LDO, is 4.2V (typical). Below either UVLO threshold,
both HDRVx and LDRVx will be turned off and the internal
MOSFETs will be turned on to discharge the output capaci-
tors through the SWx pins. As the input voltage increases
again above 4.2V, UVLO will be de-activated, and the device
will restart again from the soft start phase. If the voltage at
VLIN5 remains below 4.5V, but above the 4.2V UVLO
threshold, the device cannot be guaranteed to operate within
specification.
If the input voltage is between 4.2V and 5.2V, the VLIN5 pin
will not regulate, but will follow approximately 200mV below
the input voltage. VLIN5 can be directly connected to the
ON/UVLO pin to disable the external UVLO function. This is
especially useful if the input voltage range will cause ON/
UVLO to exceed its absolute maximum voltage rating (7V
typ.).
SOFT START
The soft start pins, SS1/2 and SS3, must each be connected
to SGND through a capacitor. If the SS capacitor is too small,
the duty cycle may increase too rapidly, causing the device
to latch off due to output voltage overshoot above the OVP
threshold. This becomes more likely in applications requiring
low output voltage, high input voltage and light load. A typical
value of approximately 10nF is recommended.
The size of the soft start capacitors controls the ramp up rate
of the output voltages. As the input voltage rises or the
ON/UVLO pin rises above 1.9V, an internal 2µA current
charges the soft start capacitor. During soft start, the error
amplifier output voltage is clamped and the duty cycle is
controlled only by the soft start voltage. As the SSx pin
voltage ramps up, the duty cycle increases proportional to
the soft start ramp, causing the output voltage to ramp up.
The rate at which the duty cycle increases depends on the
capacitance of the soft start capacitor. The higher the ca-
pacitance, the slower the output voltage ramps up. When the
corresponding output voltage exceeds 98% (typical) of the
target voltage, the regulator switches from soft start to nor-
mal operating mode. At this time, the error amplifier clamp
releases and feedback control takes over. The soft start
capacitor value can be calculated with the following equa-
tion:
Where t is the desired ramp-up time for the output voltage
and Vnom is the target output voltage. Vpeak equals 2V for
channels 1 and 2 and 1V for channel 3. When a fault occurs,
the SSx pins are pulled low by a 5µA current sink. The device
will not restart until the fault is reset and both SSx pins are
IN
allows the user to set a secondary
15
below 80mV (typical). During soft start, over-voltage protec-
tion, prot-in1, prot-in2, under-voltage protection and current
limit remain in effect.
SEQUENTIAL STARTUP
Channel 3 is designed to start only after the delay pin
(TD12-3) has reached its threshold. When channels 1 and 2
begin softstart, TD12-3 begins sourcing current (10µA typi-
cal). A capacitor from TD12-3 to SGND is used to set the
delay time for channel 3 turn-on. Once TD12-3 has reached
its threshold, SS3 begins sourcing current and the channel 3
output begins ramping up.
OVER VOLTAGE PROTECTION (OVP)
If the output voltage on any channel rises above 110%
(typical) of nominal, over voltage protection activates and all
channels will latch off. There is a 10 µs delay between an
over voltage event on channel 1 or 2 and latch off. When the
OVP latch is set, the high side FET drivers, HDRVx, are
immediately turned off and the low side FET drivers, LDRVx,
are turned on to discharge the output capacitors through the
inductors. To reset the OVP latch, either the input voltage
must be cycled, or the device must be shut down at the
ON/UVLO pin.
UNDER VOLTAGE PROTECTION (UVP)
If the output voltage on any channel falls below 80% (typical)
of nominal, under voltage protection activates. An under-
voltage event will shut off the FAULT_DELAY MOSFET,
which will allow the FAULT_DELAY capacitor to charge at
5µA (typical). When the capacitor charges to the FAULT_DE-
LAY threshold (2V typical) all channels will latch off. FAULT-
_DELAY will then be disabled and discharged to 0V. When
the UVP latch is set, both the high side and low side FET
drivers will be turned off, and the output capacitors will be
discharged through the internal MOSFET. If the fault condi-
tion is removed before the FAULT_DELAY threshold is
reached, the pin will be discharged. To reset the UVP latch,
either the input voltage must be cycled, or the device must
be shut down. The UVP feature can be disabled by ground-
ing the FAULT_DELAY pin.
NOTE: The FAULT_DELAY time must be greater than Tss1/
2+Tss3+TD12-3. If it is not, the device will latch off due to an
under voltage condition during startup. The FAULT_DELAY
function becomes immediately active above the UVLO
threshold, and is therefore active during soft start.
COMPARATOR INPUT PROTECTION
The LM2648 features two PROT-IN pins, which can be used
for any user defined protection scheme. When PROT-IN1
rises above 1.239V (typical), this sets the PROT-IN1 latch
and shuts down the device. PROT-IN2 has a TTL/CMOS
compatible input threshold with hysteresis. This pin also
sinks a constant 2 µA (typical) current. A PROT-IN2 fault will
activate FAULT_DELAY (see Under Voltage Protection) and
can thus be deactivated by connecting FAULT_DELAY to
SGND.
The protection latches will turn off both the high and low side
FET drivers and will turn on the internal MOSFETs to dis-
charge the output capacitors through the switch nodes. Like
the UVP and OVP latches, both PROT-IN latches can only
be reset by shutting down the device, or by cycling the input
voltage.
www.national.com