MAX1064 Maxim Integrated Products, MAX1064 Datasheet - Page 8

• Manufacturer Part Number: MAX1064
• Description: (MAX1060 / MAX1064) 10-Bit ADCs
• Manufacturer: Maxim Integrated Products

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400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
8
MAX1060
_______________________________________________________________________________________
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
8
9
PIN
MAX1064
10
11
12
13
14
—
—
—
—
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
REFADJ
V
NAME
D1/D9
D0/D8
HBEN
COM
GND
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
LOGIC
CLK
REF
V
INT
WR
RD
D7
D6
D5
D4
D3
D2
CS
DD
High Byte Enable. Used to multiplex the 10-bit conversion result.
1: 2 MSBs are multiplexed on the data bus.
0: 8 LSBs are available on the data bus.
Tri-State Digital I/O Line (D7)
Tri-State Digital I/O Line (D6)
Tri-State Digital I/O Line (D5)
Tri-State Digital I/O Line (D4)
Tri-State Digital I/O Line (D3)
Tri-State Digital I/O Line (D2)
Tri-State Digital I/O Line (D1, HBEN = 0; D9, HBEN = 1)
Tri-State Digital I/O Line (D0, HBEN = 0; D8, HBEN = 1)
INT goes low when the conversion is complete and the output data is ready.
Active-Low Read Select. If CS is low, a falling edge on RD enables the read operation on the
data bus.
Active-Low Write Select. When CS is low in internal acquisition mode, a rising edge on WR
latches in configuration data and starts an acquisition plus a conversion cycle. When CS is
low in external acquisition mode, the first rising edge on WR ends acquisition and starts a
conversion.
Clock Input. In external clock mode, drive CLK with a TTL-/CMOS-compatible clock. In inter-
nal clock mode, connect this pin to either V
Active-Low Chip Select. When CS is high, digital outputs (D7–D0) are high impedance.
Analog Input Channel 7
Analog Input Channel 6
Analog Input Channel 5
Analog Input Channel 4
Analog Input Channel 3
Analog Input Channel 2
Analog Input Channel 1
Analog Input Channel 0
Ground Reference for Analog Inputs. Sets zero-code voltage in single-ended mode and
must be stable to ±0.5 LSB during conversion.
Analog and Digital Ground
Bandgap Reference Output/Bandgap Reference Buffer Input. Bypass to GND with a 0.01µF
capacitor. When using an external reference, connect REFADJ to V
bandgap reference.
Bandgap Reference Buffer Output/External Reference Input. Add a 4.7µF capacitor to GND
when using the internal reference.
Analog +5V Power Supply. Bypass with a 0.1µF capacitor to GND.
Digital Power Supply. V
from +2.7V to (V
DD
+ 300mV).
LOGIC
powers the digital outputs of the data converter and can range
FUNCTION
DD
or GND.
Pin Description
DD
to disable the internal