MAX11040 Maxim Integrated Products, MAX11040 Datasheet - Page 18

• Manufacturer Part Number: MAX11040
• Description: Sigma-Delta ADC
• Manufacturer: Maxim Integrated Products

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Table 5. Data Register (EN24BIT = 0)
Table 6. Data Register (EN24BIT = 1)
24-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADC
The Data register contains the results of the ADC con-
version. The result is reported in two’s complement for-
mat. The register contains one or two pieces of
information, depending on the state of EN24BIT in the
Configuration register. When EN24BIT is set to zero, the
Data register contains the ADC data truncated to 19
bits, followed by the device and channel addresses
18
[95:77]
[76:74]
[73:72]
[71:53]
[52:50]
[49:48]
[47:29]
[28:26]
[25:24]
[95:72]
[71:48]
[47:24]
[23:5]
[23:0]
[4:2]
[1:0]
BIT
BIT
______________________________________________________________________________________
CH0DATA[18:0]
CH1DATA[18:0]
CH2DATA[18:0]
CH3DATA[18:0]
CH0DATA[23:0]
CH1DATA[23:0]
CH2DATA[23:0]
CH3DATA[23:0]
IC[2:0]
IC[2:0]
IC[2:0]
IC[2:0]
NAME
NAME
00
01
10
11
Channel 0 19-bit conversion result (two’s complement)
Device address tag. IC[2:0] starts with 000 for the device nearest the master.
Channel 0 address tag = 00
Channel 1 19-bit conversion result (two’s complement)
Device address tag. IC[2:0] starts with 000 for the device nearest the master.
Channel 1 address tag = 01
Channel 2 19-bit conversion result (two’s complement)
Device address tag. IC[2:0] starts with 000 for the device nearest the master.
Channel 2 address tag = 10
Channel 3 19-bit conversion result (two’s complement)
Device address tag. IC[2:0] starts with 000 for the device nearests the master.
Channel 3 address tag = 11
Channel 0 24-bit conversion result (two’s complement)
Channel 1 24-bit conversion result (two’s complement)
Channel 2 24-bit conversion result (two’s complement)
Channel 3 24-bit conversion result (two’s complement)
Data Register
(see Table 5). When EN24BIT is set to one, the data
contained in the Data register represents the 24-bit
conversion (see Table 6). The data length of the Data
register is 96 bits for each cascaded device. Figure 11
shows the sequence of the conversion result output of
all channels for two cascaded devices.
If the results are not read back prior to completion of
the next conversion, the data is overwritten.
DESCRIPTION
DESCRIPTION