MAX1124 Maxim Integrated Products, MAX1124 Datasheet - Page 8

• Manufacturer Part Number: MAX1124
• Description: 250Msps Analog-to-Digital Converter
• Manufacturer: Maxim Integrated Products

1.8V, 10-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
8
(AV
tions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential R
2, 5, 7, 10, 15, 16,
18, 19, 21, 24, 64,
1, 6, 11–14, 20,
CC
_______________________________________________________________________________________
25, 62, 63, 65
66, 67, EP
= OV
PIN
17
22
23
3
4
8
9
CC
L
= 100Ω, T
= 1.8V, AGND = OGND = 0, f
SINAD vs. CLOCK DUTY CYCLE (f
60
59
58
57
56
55
54
53
52
51
50
30
f
SAMPLE
A
REFADJ
CLKDIV
= +25°C.)
NAME
AGND
REFIO
AV
CLKP
CLKN
36
INN
INP
= 249.856MHz, A
CC
CLOCK DUTY CYCLE (%)
42
48
Analog Supply Voltage. Bypass each pin with a 0.1µF capacitor for best decoupling results.
Analog Converter Ground. Connect the converter’s exposed paddle (EP) to AGND.
Reference Input/Output. With REFADJ pulled high through a 1kΩ resistor, this I/O port allows
an external reference source to be connected to the MAX1124. With REFADJ pulled low
through the same 1kΩ resistor, the internal 1.23V bandgap reference is active.
Reference-Adjust Input. REFADJ allows for full-scale range adjustments by placing a resistor
or trim potentiometer between REFADJ and AGND (decreases FS range) or REFADJ and
REFIO (increases FS range). If REFADJ is connected to AV
internal reference can be overdriven with an external source connected to REFIO. If REFADJ
is connected to AGND through a 1kΩ resistor, the internal reference is used to determine the
full-scale range of the data converter.
Positive Analog Input Terminal
Negative Analog Input Terminal
Clock Divider Input. This LVCMOS-compatible input controls which speed the converter’s
digital outputs are updated. CLKDIV has an internal pulldown resistor.
CLKDIV = 0: ADC updates digital outputs at one-half the input clock rate.
CLKDIV = 1: ADC updates digital outputs at the input clock rate.
True Clock Input. This input requires an LVDS-compatible input level to maintain the
converter’s excellent performance.
Complementary Clock Input. This input requires an LVDS-compatible input level to maintain
the converter’s excellent performance.
54
IN
60
IN
= -0.5dBFS)
SAMPLE
= 1.8148MHz,
Typical Operating Characteristics (continued)
66
72
= 250.0057MHz, -0.5dBFS; see TOCs for detailed information on test condi-
-100
FUNCTION
-40
-50
-60
-70
-80
-90
5
f
f
NPR = 54.8dB
SAMPLE
NOTCH
10
ANALOG INPUT FREQUENCY (MHz)
NOISE POWER RATIO PLOT
= 28.8MHz
= 250MHz
15
CC
20
through a 1kΩ resistor, the
25
Pin Description
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30
35