MAX1185 Maxim, MAX1185 Datasheet - Page 5

• Manufacturer Part Number: MAX1185
• Description: Dual 10-Bit / 20Msps / +3V / Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs
• Manufacturer: Maxim

ELECTRICAL CHARACTERISTICS (continued)
(V
a 10kΩ resistor, V
T
Note 1: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dB FS referenced to a +1.024V full-scale
Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is
Note 3: Digital outputs settle to V
Note 4: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.
Note 5: Equivalent dynamic performance is obtainable over full OV
POWER REQUIREMENTS
Analog Supply Voltage Range
Output Supply Voltage Range
Analog Supply Current
Output Supply Current
Power Dissipation
Power-Supply Rejection Ratio
TIMING CHARACTERISTICS
CLK Rise to CHA Output Data
Valid
CLK Fall to CHB Output Data
Valid
Clock Rise/Fall to A/B Rise/Fall
Time
Output Enable Time
Output Disable Time
CLK Pulse Width High
CLK Pulse Width Low
Wake-Up Time
CHANNEL-TO-CHANNEL MATCHING
Crosstalk
Gain Matching
Phase Matching
A
Internal Reference and Multiplexed Parallel Outputs
DD
= T
= +3V, OV
MIN
input voltage range.
6dB or better, if referenced to the two-tone envelope.
to T
PARAMETER
Dual 10-Bit, 20Msps, +3V, Low-Power ADC with
MAX
DD
, unless otherwise noted. Typical values are at T
= +2.5V, 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through
_______________________________________________________________________________________
IN
= 2Vp-p (differential w.r.t. COM), C
IH
, V
SYMBOL
t
t
DISABLE
ENABLE
PDISS
IL
OV
I
t
PSRR
t
OVDD
t
t
WAKE
I
V
DA/B
DOA
DOB
t
VDD
t
. Parameter guaranteed by design.
CH
CL
DD
DD
Operating, f
Sleep mode
Shutdown, clock idle, PD = OE = OV
Operating, C
-0.5dB FS
Sleep mode
Shutdown, clock idle, PD = OE = OV
Operating, f
Sleep mode
Shutdown, clock idle, PD = OE = OV
Offset
Gain
Figure 3 (Note 3)
Figure 3 (Note 3)
Figure 4
Figure 4
Figure 3, clock period: 50ns
Figure 3, clock period: 50ns
Wakeup from sleep mode (Note 4)
Wakeup from shutdown (Note 4)
f
f
f
INA or B
INA or B
INA or B
= 7.5MHz at -0.5dB FS
= 7.5MHz at -0.5dB FS
= 7.5MHz at -0.5dB FS
INA or B
INA or B
L
= 15pF, f
CONDITIONS
A
DD
= +25°C.)
= 7.5MHz at -0.5dB FS
= 7.5MHz at -0.5dB FS
L
range with reduced C
= 10pF at digital outputs (Note 5), f
INA or B
= 7.5MHz at
DD
DD
DD
L
.
MIN
2.7
1.7
25 ± 7.5
25 ± 7.5
TYP
±0.2
±0.1
0.51
0.02
0.25
100
105
3.0
2.5
2.8
8.4
1.5
1.5
-70
35
10
1
4
2
3
5
5
6
CLK
MAX
±0.2
150
3.6
3.6
50
15
10
45
8
8
= 20MHz,
d eg r ees
UNITS
mV/V
%/V
mW
mA
mA
µW
µA
µA
dB
dB
ns
ns
ns
ns
ns
ns
ns
µs
V
V
5