MAX500 Maxim Integrated Products, MAX500 Datasheet - Page 6

• Manufacturer Part Number: MAX500
• Description: CMOS, Quad, Serial Interface 8-Bit DAC
• Manufacturer: Maxim Integrated Products

sink, as well as source up to 5mA. This is especially
important in single-supply applications, where V
connected to AGND, so that the zero error is kept at or
under 1/2LSB (V
Current vs. Output Voltage is shown in the Typical
Operating Characteristics section.
The digital inputs are compatible with both TTL and 5V
CMOS logic; however, the power-supply current (I
is somewhat dependent on the input logic level. Supply
current is specified for TTL input levels (worst case) but
is reduced (by about 150µA) when the logic inputs are
driven near DGND or 4V above DGND.
Do not drive the digital inputs directly from CMOS logic
running from a power supply exceeding 5V. When driv-
CMOS, Quad, Serial-Interface
8-Bit DAC
Figure 2. Positive and Negative Settling Times
Figure 3. Dynamic Response
6
_______________________________________________________________________________________
REF
(V
POSITIVE STEP
DYNAMIC RESPONSE
SS
(V
1 s/div
= -5V or 0V)
SS
= +10V). A plot of the Output Sink
= -5V or 0V)
2 s/div
and Interface Logic
LDAC
5V/div
OUTPUT
100mV/div
Digital Inputs
LDAC
5V/div
OUTPUT
5V/div
SS
DD
(20mV/div)
is
OUTPUT
)
(5V/div)
INPUT
ing SCL through an opto-isolator, use a Schmitt trigger
to ensure fast SCL rise and fall times.
The MAX500 allows the user to choose between a
3-wire serial interface and a 2-wire serial interface.
The choice between the 2-wire and the 3-wire inter-
face is set by the LOAD signal. If the LOAD is allowed
to float (it has a weak internal pull-up resistor to V
the 2-wire interface is selected. If the LOAD signal is
kept to a TTL-logic high level, the 3-wire interface
is selected.
The 3-wire interface uses the classic Serial Data (SDA),
Serial Clock (SCL), and LOAD signals that are used
in standard shift registers. The data is clocked in on
the falling edge of SCL until all 10 bits (8 data bits and
2 address bits) are entered into the shift register.
Figure 4. Simplified Output Buffer Circuit
V
V
DD
SS
INVERTED
OUTPUT
FROM
DAC
INPUTS
(+)
PMOS
(V
NEGATIVE STEP
SS
1 s/div
= -5V or 0V)
(-)
C
C
3-Wire Interface
LDAC
5V/div
OUTPUT
100mV/div
PULL-DOWN
FOLLOWER
EMITTER
PULL-UP
CIRCUIT
ACTIVE
NMOS
NPN
V
OUT
DD
),