MAX1204 Maxim, MAX1204 Datasheet - Page 7

• Manufacturer Part Number: MAX1204
• Description: 5v / 8-cHANNEL / sERIAL / 10-bIT adc WITH 3v dIGITAL iNTERFACE
• Manufacturer: Maxim

(V
4.7µF capacitor at REF; T
__________________________________________Typical Operating Characteristics
______________________________________________________________Pin Description
DD
PIN
1–8
2.0
1.8
1.6
1.4
1.2
1.0
10
11
12
13
14
15
16
17
18
19
20
9
= 5V ±5%; VL = 2.7V to 3.6V; f
4.5
4.7
CH0–CH7
vs. SUPPLY VOLTAGE
REFADJ
SUPPLY VOLTAGE (V)
SSTRB
NAME
SHDN
DOUT
SUPPLY CURRENT
SCLK
GND
REF
V
V
DIN
CS
VL
DD
SS
4.9
_______________________________________________________________________________________
A
5.1
= +25°C; unless otherwise noted.)
Sampling Analog Inputs
Negative Supply Voltage. Tie V
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1204 down to 10µA (max) supply
current; otherwise, the MAX1204 is fully operational. Pulling SHDN to V
amplifier in internal compensation mode. Letting SHDN float puts the reference-buffer amplifier in
external compensation mode.
Reference Buffer Output/ADC Reference Input. In internal reference mode, the reference buffer
provides a 4.096V nominal output, externally adjustable at REFADJ. In external reference mode,
disable the internal buffer by pulling REFADJ to V
Input to the Reference-Buffer Amplifier. Tie REFADJ to V
Ground; IN- Input for Single-Ended Conversions
Supply Voltage for Digital Output Pins. Voltage applied to VL determines the positive output swing of
the Digital Outputs (DOUT, SSTRB).
Serial-Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CS is high.
Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX1204 begins the analog-
to-digital conversion and goes high when the conversion is finished. In external clock mode, SSTRB
pulses high for one clock period before the MSB decision. High impedance when CS is high (external
clock mode).
Serial-Data Input. Data is clocked in at SCLK’s rising edge.
Active-Low Chip Select. Data is not clocked into DIN unless CS is low. When CS is high, DOUT is
high impedance.
Serial-Clock Input. SCLK clocks data in and out of serial interface. In external clock mode, SCLK also
sets the conversion speed. (Duty cycle must be 40% to 60% in external clock mode.)
Positive Supply Voltage, +5V ±5%
5.3
SCLK
5.5
= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);
5V, 8-Channel, Serial, 10-Bit ADC
2.0
1.8
1.6
1.4
1.2
1.0
-60
-20
vs. TEMPERATURE
SS
SUPPLY CURRENT
TEMPERATURE (°C)
to -5V ±5% or GND.
with 3V Digital Interface
20
60
FUNCTION
100
DD.
140
DD
to disable the reference-buffer amplifier.
6
5
4
3
2
1
0
-60
REFADJ = GND
DD
SHUTDOWN SUPPLY CURRENT
-20
puts the reference-buffer
vs. TEMPERATURE
TEMPERATURE ( C)
20
60
100
140
7