MAX1270ACAI Maxim, MAX1270ACAI Datasheet - Page 12

• Manufacturer Part Number: MAX1270ACAI
• Description: Multirange / +5V / 8-Channel / Serial 12-Bit ADCs
• Manufacturer: Maxim

Input data (control byte) is clocked in at DIN at the ris-
ing edge of SCLK. CS enables communication with the
MAX1270/MAX1271. After CS falls, the first arriving
logic 1 bit represents the start bit (MSB) of the input
control byte. The start bit is defined as:
Output data is clocked out on the falling edge of SCLK
at DOUT, MSB first (D11). In unipolar mode, the output
is straight binary. For bipolar mode, the output is two’s
complement binary. For output binary codes, refer to
the Transfer Function section.
The MAX1270/MAX1271 use either an external serial
clock or the internal clock to complete an acquisition
and perform a conversion. In both clock modes, the
external clock shifts data in and out. See Table 4 for
details on programming clock modes.
The falling edge of CS does not start a conversion on
the MAX1270/MAX1271; a control byte is required for
each conversion. Acquisition starts after the sixth bit is
programmed in the input control byte. Conversion
starts when the acquisition time, six clock cycles,
expires.
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
Figure 6. External Clock Mode—25 Clocks/Conversion Timing
12
The first high bit clocked into DIN with CS low
anytime the converter is idle; e.g., after V
applied.
The first high bit clocked into DIN after bit 6
(D6) of a conversion in progress is clocked
onto DOUT.
______________________________________________________________________________________
SSTRB
DOUT
A/D STATE
SCLK
DIN
CS
HIGH-Z
HIGH-Z
START SEL2 SEL1 SEL0
MSB
1
OR
How to Start a Conversion
Output Data Format
RNG
Input Data Format
BIP
PD1
DD
PD0
LSB
is
8
ACQUISITION
6 SCLK
Keep CS low during successive conversions. If a start-
bit is received after CS transitions from high to low, but
before the output bit 6 (D6) becomes available, the cur-
rent conversion will terminate and a new conversion will
begin.
In external clock mode, the clock shifts data in and out
of the MAX1270/MAX1271 and controls the acquisition
and conversion timings. When acquisition is done,
SSTRB pulses high for one clock cycle and conversion
begins. Successive-approximation bit decisions appear
at DOUT on each of the next 12 SCLK falling edges
(Figure 6). Additional SCLK falling edges will result in
zeros appearing at DOUT. Figure 7 shows the SSTRB
timing in external clock mode.
SSTRB and DOUT go into a high-impedance state
when CS goes high; after the next CS falling edge,
SSTRB and DOUT will output a logic low.
The conversion must be completed in some minimum
time, or droop on the sample-and-hold capacitors may
degrade conversion results. Use internal clock mode if
the clock period exceeds 10µs, or if serial-clock inter-
ruptions could cause the conversion interval to exceed
120µs. The fastest the MAX1270/MAX1271 can run is
18 clocks per conversion in external clock mode, and
with a clock rate of 2MHz, the maximum sampling rate
is 111 ksps (Figure 8). In order to achieve maximum
throughput, keep CS low, use external clock mode with
a continuous SCLK, and start the following control byte
after bit 6 (D6) of the conversion in progress is clocked
onto DOUT.
If CS is low and SCLK is continuous, guarantee a start
bit by first clocking in 18 zeros.
12
13
MSB
D11
14
CONVERSION
12 SCLK
D10
External Clock Mode (PD1 = 0, PD0 = 1)
D9
D1
24
D0
LSB
25
FILLED WITH
ZEROS
HIGH-Z
HIGH-Z