MAX1464 Maxim, MAX1464 Datasheet - Page 21

• Manufacturer Part Number: MAX1464
• Description: Low-Power - Low-Noise Multichannel Sensor Signal Processor
• Manufacturer: Maxim

1) Halt the CPU:
2) If partition 1 is to be modified, enter the following
3) Turn off all analog modes:
4) For erasing the whole partition, send the following
5) Wait at least 4.2ms before sending any other
6) Write the address of the FLASH byte to be written
7) Write the contents of the byte to DHR[7:0]:
8) Send the command to execute the FLASH write:
78
command:
F8
Otherwise, partition 0 is selected.
03 02 01 00
D4
08
03 02 31 10
E4
08
83 02 01 00
F4
08
At this point, all the MAX1464 analog modules are off.
command:
E8
Otherwise, if only a page erase is required, first write
PFAR[11:6] with the page address, as:
07 X6 X5 04
Note that the 2 lower bits of PFAR[7:4] should be
zero, and only the upper 2 bits of that nibble should
be set to the desired value. Then, after writing the
page address, send the page-erase command:
D8
command to allow the necessary time for the
erase operation to complete.
to PFAR[15:0]:
07 X6 X5 X4
X1 X0
18
______________________________________________________________________________________
(write 0000h to DHR[15:0])
(write Dh to PFAR[3:0])
(write DHR, 1000h to CPU port
pointed by PFAR[3:0], port D)
(write 0031h to DHR[15:0])
(write Eh to PFAR[3:0])
(write DHR, 0031h to CPU port
pointed by PFAR[3:0], port E)
(write 8000h to DHR[15:0])
(write Fh to PFAR[3:0])
(write DHR, 8000h to CPU port
pointed by PFAR[3:0], port F)
(write 0XX0h to PFAR[15:0])
(write 0XXXh to PFAR[15:0])
(write XXh to DHR[7:0], high nibble
at DHR[7:4])
Low-Power, Low-Noise Multichannel
Sensor Signal Processor
9) Repeat steps 6, 7, and 8 for all the bytes to be
10) If partition 1 was selected in step 2, and the user
The procedure to read the FLASH contents is no different
from reading any other information from the MAX1464.
The FLASH contents must be copied to the DHR and
read through the serial interface:
1) If the CPU is not halted, halt the CPU:
2) If partition 1 is to be read, enter the following
3) Write the address of the flash byte to be read to
4) Copy the contents of FLASH addressed by PFAR to
5) If the interface is configured in 3-wire mode, send
6) Repeat steps 3, 4, and 5 for every byte to be read.
written. It is not necessary to send the whole
address and data for every byte that is written. Only
the nibbles that are modified in the PFAR and in the
DHR from previous values must be changed. The
time interval between successive write commands
(18h) must be at least 80µs.
wants to switch back to partition 0, send the follow
ing command:
78
At this point, partition 0 is selected. The user may
want to go back to step 4 to program partition 0, or
just continue on.
78
command:
F8
Otherwise, partition 0 is selected.
PFAR[15:0]:
07 X6 X5 X4
DHR:
38
19
to enable DO on the next CS cycle. Then tri-
state the DI driver, and send 16 SCLK pulses on
the following CS cycle, and DO outputs DHR[15:0].
The FLASH data is present at DHR[7:0]. See Figure
10 for details.
If the interface is configured in 4-wire mode, there
is no need to enable the DO line, as it has already
been enabled by a previous IRS command 09h.
Send the 16 SCLK pulses and retrieve the data on
the DO line.
Only the nibbles that are modified in the PFAR reg-
ister are required to be sent.
(write 0XXXh to PFAR[15:0])
Reading the FLASH Contents
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