MAX16039 Maxim Integrated Products, MAX16039 Datasheet - Page 9

• Manufacturer Part Number: MAX16039
• Description: (MAX16033 - MAX16040) Low-Power Battery Backup Circuits
• Manufacturer: Maxim Integrated Products

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The Typical Operating Circuit shows a typical connec-
tion for the MAX16033–MAX16040. OUT powers the
static random-access memory (SRAM). If V
greater than the reset threshold (V
than V
OUT. If V
V
200mA from V
MOSFET connects the backup battery to OUT. The on-
resistance of the MOSFET is a function of the backup-
battery voltage and temperature and is shown in the
BATT-to-OUT On-Resistance vs. Temperature graph in
the Typical Operating Characteristics .
The MAX16033–MAX16036 provide internal gating of
chip-enable (CE) signals to prevent erroneous data
from being written to CMOS RAM in the event of a
power failure or brownout condition. During normal
operation, the CE gate is enabled and passes all CE
transitions. When reset asserts, this path becomes
disabled, preventing erroneous data from corrupting
the CMOS RAM. The MAX16033–MAX16036 provide a
series transmission gate from CEIN to CEOUT. A 2ns
(typ) propagation delay from CEIN to CEOUT allows
Figure 1. RESET and Chip-Enable Timing
BATT
, BATT is connected to OUT. OUT supplies up to
TH
PFI > V
CC
RESET
but higher than V
CEOUT
CEIN
V
PFO
V
CC
TH
PFI
is lower than V
CC
. In battery-backup mode, an internal
(MAX16033–MAX16036 Only)
_______________________________________________________________________________________
Chip-Enable Signal Gating
Detailed Description
BATT
TH
RESET-TO-CEOUT DELAY
, V
and V
TH
CC
Circuits in Small µDFN Packages
), or if V
is connected to
CC
t
RD
is less than
CC
is lower
CC
Low-Power Battery Backup
is
these devices to be used with most µPs and high-
speed DSPs.
When RESET is deasserted, CEIN is connected to
CEOUT through a low on-resistance transmission gate.
If CEIN is high when RESET is asserted, CEOUT
remains high regardless of any subsequent transitions
on CEIN during the reset event.
If CEIN is low when RESET is asserted, CEOUT is held
low for 1µs to allow completion of the read/write opera-
tion (Figure 1). After the 1µs delay expires, CEOUT
goes high and stays high regardless of any subsequent
transitions on CEIN during the reset event. When
CEOUT is disconnected from CEIN, CEOUT is actively
pulled up to OUT.
The propagation delay through the chip-enable circuit-
ry depends on both the source impedance of the drive
to CEIN and the capacitive loading at CEOUT. The
chip-enable propagation delay is specified from the
50% point of CEIN to the 50% point of CEOUT, using a
50Ω driver and 50pF load capacitance. Minimize the
capacitive load at CEOUT and use a low output-imped-
ance driver to minimize propagation delay.
In high-impedance mode, the leakage current at CEIN
is ±1µA (max) over temperature. In low-impedance
mode, the impedance of CEIN appears as a 75Ω resis-
tor in series with the load at CEOUT.
t
RP
*
CEOUT GOES HIGH WITHOUT DELAY AS CEIN GOES HIGH.
IF CEIN GOES HIGH BEFORE RESET ASSERTS,
t
RD
*
t
RP
9