ATA5279 ATMEL Corporation, ATA5279 Datasheet - Page 17

• Manufacturer Part Number: ATA5279
• Manufacturer: ATMEL Corporation

3.8
3.8.1
3.8.2
9125A–RKE–04/08
Command Buffer
Structure
Usage
This buffer is a First-In-First-Out (FIFO)-type buffer, located between the SPI and the modulator
stage. The microcontroller can write coil-driving related commands and data with full SPI speed
to keep the CPU and bus load low.
The buffer can store up to 128 bits, organized in 16 words, each eight bit in size. Hence, each
data word from the SPI that contains a control command for the driver stages (i.e., select a cer-
tain driver, select a certain current, transmit LF-data bits and transmit a constant wave) is stored
in a buffer word.
Figure 3-12. Structure of 128 bit FIFO Command Buffer
The read pointer indicates the next word to be processed by the Modulator Stage, whereas the
write pointer indicates the next free location for data from the SPI. These pointers are controlled
by the internal logic to enable the first-in-first-out functionality.
After wake-up from power-down, the buffer is empty and ready to receive commands and LF
data. Any LF command and data is fed into the buffer via the SPI. The buffer can be filled even
during an active data modulation, i.e., when some LF data and/or commands remain in the
buffer while waiting to be processed. This increases the independency of the coil driver from the
microcontroller. An interrupt request (IRQ) is triggered when the fill state of the buffer drops
below 25% or if too many words are sent and a FIFO overflow occurs.
From SPI
Figure 3-12
8
General Command
Processing
Selector
Data
outlines this.
8
8
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
ATA5279 [Preliminary]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
Write Pointer
Read Pointer
Modulator Stage
17