ATA6621 ATMEL Corporation, ATA6621 Datasheet - Page 14

• Manufacturer Part Number: ATA6621
• Manufacturer: ATMEL Corporation

3.16.2
14
ATA6621
Worst Case Calculation with R
After ramping up the battery voltage, the 5V regulator is switched on. The reset output NRES
stays low for the time t
the watchdog sequence from the microcontroller. This lead time t
t
pulse NTRIG (or PTRIG, as the case may be) occurs during this time, the time t
ately. If no trigger signal occurs during the time t
reset the microcontroller after t
other. A triggering signal from the microcontroller is anticipated within the time frame of
t
t
in this open window t
ing the closed window t
Figure 3-8.
The internal oscillator has a tolerance of ±20%. This means that t
The worst case calculation for the watchdog period T
culated as follows.
The ideal watchdog time T
t
t
T
T
T
A microcontroller with an oscillator tolerance of ±15% is sufficient to supply the trigger inputs
correctly within the time period of T
d
2
trigg
1,min
2,min
wdmax
wdmin
wd
V
= 49 ms. In this time, the first watchdog pulse from the microcontroller is required. If the trigger
= 10.5 ms. To avoid false triggering from glitches, the trigger pulse must be longer than
CC
NTRIG
PTRIG
= 14.2 ms ±2.2 ms (±15%)
NRES
> 3 µs. This slope serves to restart the watchdog sequence. Should the triggering signal fail
= 0.8
= 0.8
= 5V
= t
= t
1max
1min
t
t
1
2
+ t
= 12 ms
Timing Sequence with R
t
Undervoltage Reset
= 8 ms, t
= 8.4 ms, t
reset
2min
WO_OSC
= 10 ms
= 8 ms + 8.4 ms = 16.4 ms
2
, the NRES output will be drawn to ground after t
reset
1
1,max
= 51 k
causes NRES to immediately switch low.
2,max
wd
(typically 10 ms), then it switches to high and the watchdog waits for
= 1.2
is between (t
d
= 1.2
= 49 ms. The times t
t
d
= 49 ms
wd
t
1
= 14.2 ms (±15%) in an application with R
t
= 12 ms
WD_OSC
2
t
= 12.6 ms
1
1
= 10 ms
maximum) and (t
t
trigg
= 51 k
t
> 3 µs
wd
d
, a watchdog reset with t
t
2
1
wd
= 10.5 ms
and t
the microcontroller has to provide is cal-
2
1
have a fixed relationship with each
minimum plus t
t
1
1
d
and t
follows after the reset and is
2
2
. A triggering signal dur-
can also vary by ±20%.
t
2
NRES
2
minimum).
wd_osc
Watchdog Reset
1
4887B–AUTO–01/06
starts immedi-
= 1.96 ms will
t
nres
= 51 k .
= 1.9 ms