ATA8742 ATMEL Corporation, ATA8742 Datasheet - Page 90

• Manufacturer Part Number: ATA8742
• Manufacturer: ATMEL Corporation

20.2.2
20.3
20.4
90
Timer/Counter Clock Sources
Counter Unit
ATA8742
Definitions
uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source
is selected. The output from the Clock Select logic is referred to as the timer clock (clk
The double buffered Output Compare Registers (OCR0A and OCR0B) is compared with the
Timer/Counter value at all times. The result of the compare can be used by the Waveform Gen-
erator to generate a PWM or variable frequency output on the Output Compare pins (OC0A and
OC0B). See
set the Compare Flag (OCF0A or OCF0B) which can be used to generate an Output Compare
interrupt request.
Many register and bit references in this section are written in general form. A lower case “n”
replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Com-
pare Unit, in this case Compare Unit A or Compare Unit B. However, when using the register or
bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing
Timer/Counter0 counter value and so on.
The definitions in
Table 20-1.
The Timer/Counter can be clocked by an internal or an external clock source. The clock source
is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits
located in the Timer/Counter Control Register (TCCR0B). For details on clock sources and pres-
caler, see
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.
20-2 on page 90
Figure 20-2. Counter Unit Block Diagram
BOTTOM
MAX
TOP
“Timer/Counter Prescaler” on page
“Output Compare Unit” on page 91
Definitions
DATA BUS
The counter reaches the BOTTOM when it becomes 0x00.
The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
The counter reaches the TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be assigned to be the fixed value 0xFF
(MAX) or the value stored in the OCR0A Register. The assignment is depen-
dent on the mode of operation.
shows a block diagram of the counter and its surroundings.
TCNTn
Table 20-1 on page 90
direction
count
clear
bottom
are also used extensively throughout the document.
Control Logic
136.
for details. The Compare Match event will also
top
TOVn
(Int.Req.)
clk
Tn
Clock Select
( From Prescaler )
Detector
Edge
9151A–INDCO–07/09
Tn
T0
).
Figure