ATA8743 ATMEL Corporation, ATA8743 Datasheet - Page 137
ATA8743
Manufacturer Part Number
ATA8743
Description
Manufacturer
ATMEL Corporation
Datasheet
1.ATA8743.pdf
(238 pages)
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22.1
22.1.1
9152A–INDCO–07/09
Register Description
GTCCR – General Timer/Counter Control Register
tem clock frequency (f
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than f
An external clock source can not be prescaled.
Figure 22-2. Prescaler for Timer/Counter0
Note:
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the
value that is written to the PSR10 bit is kept, hence keeping the Prescaler Reset signal asserted.
This ensures that the Timer/Counter is halted and can be configured without the risk of advanc-
ing during configuration. When the TSM bit is written to zero, the PSR10 bit is cleared by
hardware, and the Timer/Counter start counting.
• Bit 0 – PSR10: Prescaler 0 Reset Timer/Counter n
When this bit is one, the Timer/Counter prescaler will be Reset. This bit is normally cleared
immediately by hardware, except if the TSM bit is set.
Bit
0x23 (0x43)
Read/Write
Initial Value
1. The synchronization logic on the input pins (
PSR10
clk
T0
I/O
TSM
R/W
7
0
Synchronization
ExtClk
R
6
–
0
< f
clk_I/O
Clear
/2) given a 50/50% duty cycle. Since the edge detector uses
R
5
–
0
R
4
–
0
T0)
is shown in
R
3
–
0
R
2
–
0
clk
Figure 22-1 on page
T0
R
1
–
0
ATA8743
PSR10
R/W
clk_I/O
0
0
136.
/2.5.
GTCCR
137
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