MAX17000A Maxim Integrated Products, MAX17000A Datasheet - Page 27

• Manufacturer Part Number: MAX17000A
• Description: Complete DDR2 and DDR3 Memory Power-Management Solution
• Manufacturer: Maxim Integrated Products

w w w . D a t a S h e e t 4 U . c o m
For most applications, nontantalum chemistries (ceramic,
aluminum, or OS-CON) are preferred due to their resis-
tance to inrush surge currents typical of systems with a
mechanical switch or connector in series with the input.
If the Quick-PWM controller is operated as the second
stage of a two-stage power-conversion system, tanta-
lum input capacitors are acceptable. In either configu-
ration, choose an input capacitor that exhibits less than
+10°C temperature rise at the RMS input current for
optimal circuit longevity.
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
when using high-voltage (> 20V) AC adapters. Low-
current applications usually require less attention.
The high-side MOSFET (N
the resistive losses plus the switching losses at both
V
Ideally, the losses at V
losses at V
losses at V
at V
R
es at V
V
R
wide range, the minimum power dissipation occurs
where the resistive losses equal the switching losses.
Choose a low-side MOSFET that has the lowest possi-
ble on-resistance (R
package (i.e., one or two 8-pin SOs, DPAK, or D
and is reasonably priced. Make sure that the DL gate
driver can supply sufficient current to support the gate
charge and the current injected into the parasitic gate-
to-drain capacitor caused by the high-side MOSFET
turning on; otherwise, cross-conduction problems can
occur (see the MOSFET Gate Drivers (DH, DL) section).
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET (N
case power dissipation due to resistance occurs at the
minimum input voltage:
Generally, a small high-side MOSFET is desired to
reduce switching losses at high input voltages.
However, the R
power dissipation often limits how small the MOSFET
IN(MIN)
IN(MIN)
DS(ON)
DS(ON)
IN(MAX)
PD (NH Resistive) =
IN(MAX)
, consider reducing the size of N
but with higher C
to lower C
and V
IN(MIN)
, consider increasing the size of N
IN(MAX)
are significantly higher than the losses at
DS(ON)
IN(MAX)
are significantly higher than the losses
______________________________________________________________________________________
, with lower losses in between. If the
DS(ON)
GATE
IN(MIN)
⎛
⎝ ⎜
required to stay within package
. Calculate both these sums.
V
). If V
OUT
V
GATE
MOSFET Power Dissipation
H
), comes in a moderate-sized
IN
) must be able to dissipate
should be roughly equal to
⎞
⎠ ⎟
). Conversely, if the loss-
IN
MOSFET Selection
×
Complete DDR2 and DDR3 Memory
(
does not vary over a
I
LOAD
)
2
H
H
×
), the worst-
R R
H
(increasing
DS ON
(reducing
Power-Management Solution
(
2
PAK),
)
can be. Again, the optimum occurs when the switching
losses equal the conduction (R
side switching losses do not usually become an issue
until the input is greater than approximately 15V.
Calculating the power dissipation in high-side MOSFET
(N
allow for difficult quantifying factors that influence the
turn-on and turn-off times. These factors include the
internal gate resistance, gate charge, threshold voltage,
source inductance, and PCB layout characteristics. The
following switching-loss calculation provides only a very
rough estimate and is no substitute for breadboard
evaluation, preferably including verification using a
thermocouple mounted on N
where C
Q
and I
(2.2A typ).
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
voltages are applied, due to the squared term in the
C x V
MOSFET chosen for adequate R
voltages becomes extraordinarily hot when biased from
V
lower parasitic capacitance.
For the low-side MOSFET (N
dissipation always occurs at maximum input voltage:
The worst case for MOSFET power dissipation occurs
under heavy overloads that are greater than
I
the current limit and cause the fault latch to trip. To pro-
tect against this possibility, the circuit can be “over
designed” to tolerate:
PD (NL Resistive) = 1−
LOAD(MAX)
IN(MAX)
G(SW)
PD (NH Switching) = V
H
) due to switching losses is difficult since it must
GATE
IN
I
LOAD
2
is the charge needed to turn on the N
OSS
x f
, consider choosing another MOSFET with
, but are not quite high enough to exceed
is the peak gate-drive source/sink current
SW
=
=
is the N
⎛
⎝ ⎜
I
switching-loss equation. If the high-side
VALLEY MAX
I
VALLEY MAX
+
⎡
⎢
⎢
⎣
C
H
O
(
IN MAX
⎛
⎜
⎝
(
S S S
MOSFET’s output capacitance,
V
(
IN MAX
V
×
OUT
)
(
)
V
+
H
2
)
IN
+
:
L
⎛
⎜
⎝
×
2
), the worst-case power
Δ
I
LOAD MAX
)
I
LOAD
I
⎞
⎟
⎠
×
INDUCTOR
DS(ON)
DS(ON)
⎤ ⎤
⎥
⎥
⎦
f
SW
×
2
(
(
I
LOAD
×
2
f
SW
) losses. High-
)
at low battery
×
⎞
⎠ ⎟
)
⎛
⎜
⎝
2
LIR
H
Q
I
×
GATE
G SW
MOSFET,
R
⎞
⎟
⎠
(
DS ON
(
) )
⎞
⎟
⎠
27
)