MAX1711 Maxim, MAX1711 Datasheet - Page 16

• Manufacturer Part Number: MAX1711
• Description: High-Speed / Digitally Adjusted Step-Down Controllers for Notebook CPUs
• Manufacturer: Maxim

High-Speed, Digitally Adjusted
Step-Down Controllers for Notebook CPUs
Table 3. Operating Mode Truth Table
Table 4. Frequency Selection Guidelines
DL is also kept high continuously when V
active as well as in Shutdown1 mode (Table 3).
Overvoltage protection can be defeated via the OVP
input (MAX1710 only) or via a SKIP test
Description ).
The output undervoltage protection function is similar to
foldback current limiting, but employs a timer rather than
16
FREQUENCY
SHDN
0
0
1
1
1
1
1
1
(kHz)
200
300
400
550
______________________________________________________________________________________
Output Undervoltage Protection (UVP)
Below
SKIP
GND
GND
V
X
X
X
X
X
CC
4-cell Li+ notebook
CPU core
4-cell Li+ notebook
CPU core
3-cell Li+ notebook
CPU core
+5V-input notebook
CPU core
OVP
APPLICATION
X
X
X
X
X
0
1
1
TYPICAL
Switching
Switching
Switching
Switching
High
High
Low
Low
DL
Run (PWM),
Use for absolute best
efficiency.
Considered mainstream
by current standards.
Useful in 4-cell systems
for lighter loads than the
CPU or where size is key.
Good operating point for
compound buck designs
or desktop circuits.
Shutdown1
Shutdown2
Shutdown3
(PFM/PWM)
(MAX1711
Low Noise
No Fault
No OVP
MODE
only)
Fault
Run
COMMENT
mode (see Pin
CC
Low-power shutdown state. DL is forced to V
Low-power shutdown state. DL is forced to GND, disabling OVP. I
Exiting shutdown triggers a soft-start cycle.
DAC code = X1111 (see Table 2) DL is forced to PGND, DH is forced to LX. The
MAX1711 eventually goes into UVP fault mode as the load current discharges the
output.
Test mode with OVP, UVP, and thermal faults disabled and latches cleared.
Otherwise normal operation, with automatic PWM/PFM switchover for pulse
skipping at light loads (Figure 6).
OVP faults disabled and OVP latch cleared. Otherwise normal operation,
with SKIP controlling PWM/PFM switchover.
Low-noise operation with no automatic switchover. Fixed-frequency PWM action
is forced regardless of load. Inductor current reverses at light load levels.
I
Normal operation with automatic PWM/PFM switchover for pulse skipping at light
loads. I
Fault latch has been set by OVP, output UVLO, or thermal shutdown. Device will
remain in FAULT mode until V
or SHDN is toggled.
CC
UVLO is
draw = 750µA typ. I
CC
= 600µA typ. I
a variable current limit. If the MAX1710 output (FB) is
under 70% of the nominal value 20ms after coming out of
shutdown, the PWM is latched off and won’t restart until
V
MAX1711, the nominal UVP trip threshold is fixed at 0.8V.
The over/undervoltage protection features can compli-
cate the process of debugging prototype breadboards,
since there are (at most) a few milliseconds in which to
determine what went wrong. Therefore, a test mode is
provided to totally disable the OVP, UVP, and thermal
shutdown features, and clear to the fault latch if it has
been previously set. The PWM operates as if SKIP were
grounded (PFM/PWM mode).
The no-fault test mode is entered by sinking 1.5mA
from SKIP via an external negative voltage source in
series with a resistor (Figure 6). SKIP is clamped to
GND with a silicon diode, so choose the resistor value
equal to (V
Firmly establish the input voltage range and maximum
load current before choosing a switching frequency and
inductor operating point (ripple current ratio). The prima-
CC
DD
power is cycled or SHDN is toggled. For the
DD
draw = 15mA typ.
draw = load dependent.
CC
FORCE
power is cycled, SKIP is forced below ground,
COMMENTS
- 0.65V) / 1.5mA.
DD
, enforcing OVP. I
Design Procedure
No-Fault Test Mode
CC
CC
< 1µA typ.
< 1µA typ.