MAX1717 Maxim, MAX1717 Datasheet - Page 23

• Manufacturer Part Number: MAX1717
• Description: Dynamically Adjustable / Synchronous Step-Down Controller for Notebook CPUs
• Manufacturer: Maxim

the transitions relatively smooth. The average inductor
current required to make an output voltage transition is:
The overvoltage protection (OVP) circuit is designed to
protect against a shorted high-side MOSFET by draw-
ing high current and blowing the battery fuse. The out-
put voltage is continuously monitored for overvoltage. If
the output is more than 2.25V, OVP is triggered and the
circuit shuts down. The DL low-side gate-driver output
is then latched high until SKP/SDN is toggled or V
power is cycled below 1V. This action turns on the syn-
chronous-rectifier MOSFET with 100% duty and, in turn,
rapidly discharges the output filter capacitor and forces
the output to ground. If the condition that caused the
overvoltage (such as a shorted high-side MOSFET)
persists, the battery fuse will blow. DL is also kept high
continuously when V
shutdown mode (Table 5).
Figure 10. Using the Internal Mux with CPU Driving the A-Mode VID Code
*TO REDUCE QUIESCENT CURRENT, 1kΩ PULL-UP RESISTORS CAN BE REPLACED BY 1MΩ RESISTORS WITH 4.7nF CAPACATORS IN PARALLEL.
*OPTIONAL
4.7nF
I
L
Output Overvoltage Protection
Step-Down Controller for Notebook CPUs
CPU VID =
01101 → 1.35V
(A-MODE)
≅ C
______________________________________________________________________________________
CPU
OUT
CC
Dynamically Adjustable, Synchronous
UVLO is active, as well as in
· 25mV · ƒ
1M
SLEW
1k
1k
CC
3.15 TO 5.5V
1k
Overvoltage protection can be defeated through the
NO FAULT test mode (see the NO FAULT Test Mode
section).
The output UVP function is similar to foldback current
limiting, but employs a timer rather than a variable cur-
rent limit. If the MAX1717 output voltage is under 70% of
the nominal value, the PWM is latched off and won’t
restart until V
gled. To allow startup, UVP is ignored during the under-
voltage fault-blanking time (the first 256 cycles of the
slew rate after startup).
UVP can be defeated through the NO FAULT test mode
(see the NO FAULT Test Mode section).
The over/undervoltage protection features can compli-
cate the process of debugging prototype breadboards
since there are (at most) a few milliseconds in which to
determine what went wrong. Therefore, a test mode is
provided to disable totally the OVP, UVP, and thermal
shutdown features, and clear the fault latch if it has
1k
1k
B-MODE VID =
01000 → 1.6V
CC
Output Undervoltage Shutdown
100k
power is cycled or SKP/SDN is tog-
D4
D3
D2
D1
D0
NO FAULT Test Mode
MAX1717
A/B
A/B = LOW = 1.60V
A/B = HIGH = 1.35V
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