ADS-230 Datel, Inc., ADS-230 Datasheet - Page 6

• Manufacturer Part Number: ADS-230
• Description: Sampling A/D Converters
• Manufacturer: Datel, Inc.

ADS-230/ADS-231
Reference Inputs
Reference voltages are applied to the fully differential V
Since there is essentially zero current flowing through the
and V
ence ladder network is typically 750 ohms. Additional
parasitic resistances are added by the package leads, wire
bonds, conductor traces, etc. These parasitic resistances
can introduce voltage drops causing gain and offset errors
as large as 6 LSB's at the 12-bit level. These IR drops can
be compensated for by sensing the reference voltages at
the V
reference voltage an exact value as shown in Figure 4.
sense line there is negligible voltage drop to the inverting
input of the op-amp. The voltage at the inverting input of
the op-amp, therefore, accurately represents the voltage at
the top or bottom of the reference ladder network. The op-
amp drives the force input and forces the voltages at the
ends of the reference ladder network to equal the voltage
at the op-amps non-inverting input, plus or minus the op-
amps input offset voltage. When using this reference
TS
B
reference input pins. The resistance of the refer-
LM4040–4.1
and V
V
V
T
B
= 4.096V
= 0.000V
BS
1k
4.096V
0.000V
reference sense pins and forcing the
+5V
V
R
R
RLADDER = 750
R
f
S
= 0.5 (FORCE LINE IMPEDANCE)
= V
= 10 (SENSE LINE IMPEDANCE)
T
– V
0.01µF
0.01µF
B
= 4.096V
1=5.9mA
Figure 4. Ladder Reference Force and Sense Inputs
7.02V
1~0µA
1~0µA
–2.93V
1 = 5.9mA
500
500
1k
1k
T
10µF
10µF
6
0.1µF
–0.003V
V
0.1µF
V
0.1µF
V
T
B
The 0.1 and 10µF capacitors on the force inputs provide
If the ADS-230/-231 is used in a frequency domain
The reference inputs are fully differential and define the full-
V
configuration with a low offset voltage op-amp, gain and
offset errors below 0.5 LSB are readily obtainable.
high frequency decoupling of the reference ladder network.
The 500
capacitive load. The 0.01µF and 1k
stability at high frequencies. The VR/16 output should be
bypassed to analog ground with a 0.1µF ceramic capacitor.
All bypass capacitors should be located as close to the
pins as possible to minimize noise on the reference ladder.
application then the circuit shown in Figure 3 maybe used.
This circuit will introduce several LSB's of gain and offset
error, but the dynamic performance will be unaffected.
scale range of the input signal. The maximum range can be
up to 5 volts, or when required any span within the 0 to 5V
limit may be used. When using lower voltage spans the
noise performance will degrade. See the Typical
Performance Curves.
BS
TS
V
R/16
force resistors isolate the op-amp from the large
R
Rf
R
R
S
S
f
SENSE LINE
FORCE LINE
REFERENCE
LADDER
FORCE LINE
SENSE LINE
4.096V
0.000V
ADS-230/231
®
network ensures
®