ADS-325A Datel, Inc., ADS-325A Datasheet - Page 4

• Manufacturer Part Number: ADS-325A
• Description: 10-Bit,20MHz, Sampling A/D Converter
• Manufacturer: Datel, Inc.

ADS-325A
CALIBRATION FUNCTION
To achieve its superior linearity ADS-325A has an internal
calibration circuit with a built-in calibration pulse generation
circuit and an input pin for an external calibration pulse. The
calibration circuit consists of three D/A converters, a pattern
generator and an averaging circuit. With either internal or
external calibration pulses applied to the calibration circuit, the
circuit senses an offset of the x8 gain amplifier and two
reference biases supplied from the V
comparator/encoder block, and compensates them using the
three DACs.
With a single negative going calibration pulse a unit cycle of
calibration is completed. It is initiated with the negative going
edge of the calibration pulse and takes seven A/D clock
periods to be completed. Due to the fact that this calibration
cycle occupies the lower comparator for four A/D clock periods
the lower five bits of the output data remain constant through 4
clock cycles after the completion of the cycle. Figure 3 shows
the timing for the calibration cycle.
A sequence of seven unit calibration cycles initiated by seven
calibration pulses, completes a single calibration process. The
number of calibration processes required depends on the
condition of the device and on the stability of the references
and the power. Even in worst case, 80 calibration processes
done by 560 calibration pulses are enough to finish the whole
calibration.
There are three modes of the calibration function. These are:
a. Start-up calibration function
b. Internal auto-calibration function
c. External calibration function
TEST MODE = 1, LINV = 0, MINV = 0
Input Voltage
Analog
3.998V
3.996V
3.000V
2.998V
2.002V
2.000V
:
:
BIT 6 TO BIT 10
Table 1. Digital Output Coding
BIT 1 TO BIT 5
A/D CLOCK
Step
1023
1022
512
511
(MSB)
(LSB)
1
0
:
:
CAL
MSB
11
11
10
01
00
00
Digital Output Code
RT
and the V
1111
1111
0000
1111
0000
0000
:
:
1 Clock Cycle
Figure 3. Calibration Timing Diagram
RB
10ns
to a fine
1111
1110
0000
1111
0001
0000
LSB
7 Clock Cycles
N–3
N–3
N–2
N–2
4
For operation in modes a. and b. the ADS-325A has a built-in
calibration pulse generation circuit. Figure 4a. illustrates a
simplified block diagram of this circuit.
Start-up Calibration Function
At power-up of the unit the initial calibration process requires
over 600 calibration pulses. The internal start-up calibration
function automatically generates these pulses when power is
first applied to the ADS-325A. To initiate the start-up
calibration, the following five conditions must be met. See
Figure 4b.
Once all of the above conditions have been met, the calibration
pulses are generated by counting 16 A/D clock cycles on a
14-bit counter until closing the gate when the carry-out occurs.
The time required for the start-up calibration is determined by
the following formula:
where f
a clock frequency of 14.3MHz requires a calibration time of
18.3ms.
N–1
N–1
1. The supply voltage +AV
2. The voltage difference between V
3. The RESET pin (pin 15) must be set high.
4. The CE pin (pin 24) must be set low.
5. Condition 1 must be met before condition 2.
Start-up Calibration Time = 1/f
P = Positive True; N = Negative True (inverted)
MODE LINV
than AGND.
least 1 Volt.
TEST
N
1
1
1
1
0
0
0
0
CLK
4 Clock Cycles
N+1 N+2 N+3
is the frequency of the A/D clock input. For example,
N
0
1
0
1
1
0
1
0
Table 2. Digital Output Truth Table
MINV
N+4
0
0
1
1
1
1
0
0
N+5
N+5
S
must be at least 2.5 Volts higher
MSB
CLK
NN
PP
PN
NP
10
11
00
01
x 16 x 16,384
®
RT
Digital Output
and V
NNNN
NNNN
PPPP
PPPP
1010
0101
1010
0101
RB
must be at
NNNN
NNNN
LSB
PPPP
PPPP
1010
0101
1010
0101
®