MAX197 Maxim, MAX197 Datasheet - Page 10

• Manufacturer Part Number: MAX197
• Description: Multi-Range (10V / 5V / +10V / +5V) / Single +5V / 12-Bit DAS with 8+4 Bus Interface
• Manufacturer: Maxim

Conversions are initiated with a write operation, which
selects the mux channel and configures the MAX197 for
either unipolar or bipolar input range. A write pulse (WR
+ CS) can either start an acquisition interval or initiate a
combined acquisition plus conversion. The sampling
interval occurs at the end of the acquisition interval.
The ACQMOD bit in the input control byte offers two
options for acquiring the signal: internal or external.
The conversion period lasts for 12 clock cycles in either
internal or external clock or acquisition mode.
Multi-Range (±10V, ±5V, +10V, +5V),
Single +5V, 12-Bit DAS with 8+4 Bus Interface
Table 6. Data-Bus Output
Figure 5. Conversion Timing Using Internal Acquisition Mode
10
PIN
D0
D1
D2
D3
D4
D5
D6
D7
______________________________________________________________________________________
CS
WR
D7–D0
RD
HBEN
INT
DOUT
HBEN = LOW
t
B0 (LSB)
CSWS
B1
B2
B3
B4
B5
B6
B7
How to Start a Conversion
HGH-Z
t
DS
B8
B9
B10
B11 (MSB)
B11 (BIP = 1) / 0 (BIP = 0)
B11 (BIP = 1) / 0 (BIP = 0)
B11 (BIP = 1) / 0 (BIP = 0)
B11 (BIP = 1) / 0 (BIP = 0)
t
WR
t
CS
ACQMOD ="0"
CONTROL
BYTE
HBEN = HIGH
t
ACQI
t
t
DH
CSWH
t
CONV
t
D0
t
CSRS
Writing a new control byte during conversion cycle will
abort conversion and start a new acquisition interval.
Select internal acquisition by writing the control byte
with the ACQMOD bit cleared (ACQMOD = 0). This
causes the write pulse to initiate an acquisition interval
whose duration is internally timed. Conversion starts
when this six-clock-cycle acquisition interval (3µs with
f
Use the external acquisition timing mode for precise con-
trol of the sampling aperture and/or independent control
of acquisition and conversion times. The user controls
acquisition and start-of-conversion with two separate
write pulses. The first pulse, written with ACQMOD = 1,
starts an acquisition interval of indeterminate length. The
second write pulse, written with ACQMOD = 0, termi-
nates acquisition and starts conversion on WR’s rising
edge (Figure 6). However, if the second control byte
contains ACQMOD = 1, an indefinite acquisition interval
is restarted.
The address bits for the input mux must have the same
values on the first and second write pulses. Power-
down mode bits (PD0, PD1) can assume new values on
the second write pulse (see Power-Down Mode ).
CLK
t
= 2MHz) ends. See Figure 5.
INT1
HIGH / LOW
BYTE VALID
t
D01
HIGH / LOW
BYTE VALID
External Acquisition
Internal Acquisition
t
t
CSRH
TR
HGH-Z