HFC-SUSB Cologne Chip AG, HFC-SUSB Datasheet - Page 41

• Manufacturer Part Number: HFC-SUSB
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

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Name
INT_M1
INT_M2
Name
HDLC_PAR
[FIFO#]
*
For B-channels the HDLC_PAR register must be set to 00h. To use 56kbit/s restricted mode the
HDLC_PAR register must be set to 07h for B-channels.
For D-channels the HDLC_PAR register must be set to 02h.
important!
For mask bits a '1' enables and a '0' disables interrupt. RESET clears all bits to '0'.
Addr.
Addr.
1Ah
1Bh
FBh
Bits
Bits
2..0
5..3
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
6
7
r/w Function
r/w Function
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
interrupt mask for channel B1 in receive direction
interrupt mask for channel B2 in transmit direction
interrupt mask for channel B2 in receive direction
interrupt mask for channel D in transmit direction
interrupt mask for channel D in receive direction
interrupt mask for channel PCM in transmit direction
interrupt mask for channel PCM in receive direction
interrupt mask for timer
interrupt mask for processing/non processing transition
interrupt mask for GCI I-change
interrupt mask for receiver ready (RxR) of monitor channel
interrupt mask for USB interrupt
interrupt output is reversed
enable interrupt output
(number of bits to process)
'000' process 8 bits (64kbit/s) (reset default)
'001' process 1 bit
:
'111' process 7 bits (56kbit/s)
'000' start processing with bit 0 (reset default)
:
'111' start processing with bit 7
FIFO loop
'0' normal operation (reset default)
'1' repeat current frame
invert data enable/disable
'0' normal read/write data (reset default)
'1' invert data
interrupt mask for channel B1 in transmit direction
interrupt mask for TE/NT state machine state change
bit count for HDLC and transparent mode
start bit for HDLC and transparent mode
:
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Cologne
Chip
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