MAX3882 Maxim Integrated Products, MAX3882 Datasheet - Page 7

• Manufacturer Part Number: MAX3882
• Description: 2.488Gbps/2.67Gbps 1:4 Demultiplexer
• Manufacturer: Maxim Integrated Products

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The MAX3882 deserializer with clock and data recovery
and limiting amplifier converts 2.488Gbps/2.67Gbps
serial data to clean 4-bit-wide, 622Mbps/667Mbps
LVDS parallel data. The device combines a limiting
amplifier with a fully integrated phase-locked loop (PLL),
data retiming block, 4-bit demultiplexer, clock divider,
and LVDS output buffer (Figure 5). The PLL consists of a
phase/frequency detector (PFD), loop filter, and voltage-
controlled oscillator (VCO). The MAX3882 is designed to
deliver the best combination of jitter performance and
power dissipation by using a fully differential signal
architecture and low-noise design techniques.
The input signal to the device (SDI) passes through a
DC offset control block, which balances the input signal
to a zero crossing at 50%. The PLL recovers the serial
clock from the serial input data stream and produces
the properly aligned data and the buffered recovered
clock. The frequency of the recovered clock is divided
by four and converted to differential LVDS parallel out-
put PCLK. The demultiplexer generates 4-bit-wide
622Mbps/667Mbps parallel data.
The SDI inputs of the MAX3882 accept serial NRZ data
at 2.488Gbps/2.67Gbps with 10mV
amplitude. The input sensitivity is 10mV
jitter tolerance is met for a BER of 10
threshold adjust is not used. The input sensitivity is as
Clock and Data Recovery and Limiting Amplifier
PIN
EP
24
25
26
27
29
30
33
34
35
36
2.488Gbps/2.67Gbps 1:4 Demultiplexer with
Exposed Pad
RATESET
FREFSET
NAME
V
PD2+
PD3+
CAZ+
CAZ-
PD2-
PD3-
V
_______________________________________________________________________________________
CTRL
REF
Detailed Description
Negative Data Output, LVDS
Positive Data Output, LVDS
Negative Data Output, LVDS, MSB
Positive Data Output, LVDS, MSB
Sets the VCO frequency. LVTTL low for 2.488Gbps operation, high for 2.67Gbps operation.
Sets Reference Frequency. LVTTL low for 622MHz/667MHz reference, high for 155MHz/167MHz
reference.
Positive Capacitor Input for DC Offset-Cancellation Loop. Connect a 0.1µF capacitor between CAZ+
and CAZ-.
Negative Capacitor Input for DC Offset-Cancellation Loop. Connect a 0.1µF capacitor between
CAZ+ and CAZ-.
2.2V Bandgap Reference Voltage Output. Optionally used for threshold adjustment.
Analog Control Input for Threshold Adjustment. Connect to V
Ground. The exposed pad must be soldered to the circuit board ground for proper thermal and
electrical performance.
Input Amplifier
P-P
P-P
to 1600mV
-10
, at which the
when the
P-P
low as 4mV
designed to directly interface with a transimpedance
amplifier (MAX3277).
For applications when vertical threshold adjustment is
needed, the MAX3882 can be connected to the output
of an AGC amplifier (MAX3861). Here, the input voltage
range is 50mV
Procedure section for decision threshold adjust.
The phase detector in the MAX3882 produces a volt-
age proportional to the phase difference between the
incoming data and the internal clock. Because of its
feedback nature, the PLL drives the error voltage to
zero, aligning the recovered clock to the center of the
incoming data eye for retiming.
The digital frequency detector (FD) acquires frequency
lock without using an external reference clock. The fre-
quency difference between the received data and the
VCO clock is derived by sampling the in-phase and
quadrature VCO outputs on both edges of the data
input signal. Depending on the polarity of the frequency
difference, the FD drives the VCO until the frequency
difference is reduced to zero. Once frequency acquisi-
tion is complete, the FD returns to a neutral state. False
locking is eliminated by this digital frequency detector.
FUNCTION
Pin Description (continued)
P-P
for a BER of 10
P-P
CC
to 600mV
to disable threshold adjust.
Frequency Detector
P-P
-10
Phase Detector
. See the Design
. The MAX3882 is
7