WM8143-10 Wolfson Microelectronics Ltd., WM8143-10 Datasheet - Page 9

• Manufacturer Part Number: WM8143-10
• Description: WM8143 : 10 or 12-BIT, 4MSPS Analogue Front End For CCD Image Sensors
• Manufacturer: Wolfson Microelectronics Ltd.

Production Data
Device Description
S/H, Offset DACs and PGA
Each analogue input (RINP, GINP, BINP) of the
WM8143-10 consists of a sample and hold, a
programmable gain amplifier, and a DC offset
correction block. The operation of the red input stage is
summarised in Figure 2.
Figure 2 Operation of Red Input Stage
The sample/hold block can operate in two modes of
operation, CDS (Correlated Double Sampling) or Single
Ended.
In CDS operation the video signal processed is the
difference between the voltage applied at the RINP
input when RS occurs, and the voltage at the RINP
input when VS occurs. This is summarised in Figure 3.
Figure 3 Video Signal Processed in CDS mode
When using CDS the actual DC value of the input
signal is not important, as long as the signal extremes
are maintained within 0.5 volts of the chip power
supplies. This is because the signal processed is the
difference between the two sample voltages, with the
common DC voltage being rejected.
In Single Ended operation, the VS and RS control
signals occur simultaneously, and the voltage applied
to the reset switch is fixed at V
voltage processed is the difference between the voltage
applied to RINP when VS/RS occurs, and V
using Single Ended operation the DC content of the
video signal is not rejected.
The Programmable Gain Amplifier block multiplies the
resulting input voltage by a value between 0.5 and 8.25
which can be programmed independently for each of
the three input channels via the serial (or parallel)
interface.
RINP
VMID
VS
RS
S/H
S/H
RS
+
-
GAIN=G
VS
MID
. This means that the
V
Wolfson Microelectronics
OFFSET
+
VMID
MID
+
. When
V
V
RS
VS
9
Table 1 illustrates the PGA Gains Register codes
required for typical gains. (See Typical Performance
Graphs). The typical gain may also be calculated using
the following equation:
Typical Gain = 0.5+(Code .25).
Table 1 Typical Gain
The DC value of the gained signal can then be trimmed
by the 8 bit plus sign DAC. The voltage output by this
DAC is shown as V
DAC is (V
in Set-up Register 4 is set.
The output from the offset DAC stage is referenced to
the V
maximise
diagrammatically in Figure 2 by the final V
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
CODE
MID
voltage. This allows the input to the ADC to
MID
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
2.75
3
3.25
3.5
3.75
4
4.25
the
TYPICAL
/2) or 1.5*(V
GAIN
dynamic
OFFSET
MID
in Figure 2. The range of the
/2) if the DAC_RANGE bit
range,
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
CODE
WM8143-10
PD.Rev 3f June 98
and
4.5
4.75
5
5.25
5.5
5.75
6
6.25
6.5
6.75
7
7.25
7.5
7.75
8
8.25
MID
TYPICAL
is
GAIN
addition.
shown