WM8143-12 Wolfson Microelectronics Ltd., WM8143-12 Datasheet - Page 17

• Manufacturer Part Number: WM8143-12
• Description: WM8143 : 10 or 12-BIT, 4MSPS Analogue Front End For CCD Image Sensors
• Manufacturer: Wolfson Microelectronics Ltd.

Production Data
Applications Recommendations
Output Data Interface
By default, data is output from the device as a twelve-
bit wide word on OP[11:0]. Optionally, data can be
output in an eight-bit word format. Figure 15 shows this
function. Data is presented on pins OP[11:4] at twice
pixel rate.
In mode 3, the output is spread over three MCLK
periods. The first two periods contain byte A data and
the third period has byte B data. Either of the two byte
A data periods are valid.
Figure 15 Eight-bit Multiplexed Bus Output
Control Interface Selection
WM8143-12 can be controlled via a serial or parallel
interface. The decision on which interface is to be used
is made on the sense of the SEN/STB pin on the rising
edge of the NRESET signal.
Table 4 WM8143-12 Interface Set-up
It is expected that this would be achieved on system
power-up by attaching a simple RC network to the
NRESET pin. The RC network should delay the set up
SEN/STB
OP[11:4]
Ad11,d10,d9,d8,d7,d6,d5,d4 - First byte
Bd3,d2,d1,d0,PNS,CC1,CC0,ORNG - Second
byte
PNS: This bit shows if the device is configured in
parallel or serial mode. 1 = Parallel, 0 = Serial.
CC1/CC0: These bits show which channel the
current output was taken from. 00 = RED, 01 =
GREEN, 10 = BLUE.
ORNG: This bit indicates if the current output pixel
has exceeded the maximum or minimum range
during processing. 1 = out of range, 0 = within
range.
0
1
NRESET rising edge
NRESET rising edge
CONDITION
B
Serial Interface
Parallel Interface
Wolfson Microelectronics
MODE
17
on the NRESET pin until the other conditions have
been established. This feature is only activated on a
hardware reset (using the NRESET pin). The software
reset does not sample SEN/STB.
Controlling the WM8143-12
The WM8143-12 can be configured through a serial
interface or a parallel interface. Selection of the
interface type is by the SEN/STB pin which must be
tied high (parallel) or low (serial) as shown in Table 4.
Serial Interface
The serial interface consists of three pins (refer to
Figure 16). A six-bit address is clocked in MSB first
followed by an eight-bit data word, also MSB first. Each
bit is latched on the rising edge of SCK. Once the data
has been shifted into the device, a pulse is applied to
SEN to transfer the data to the appropriate internal
register.
Parallel Interface
The parallel interface uses bits [11:4] of the OP bus as
well as the STB, DNA and RNW pins (refer to Figure
17). Pin RNW must be low during a write operation.
The DNA pin defines whether the data byte is address
(low) or data (high). The data bus OP[11:4] is latched
in during the low period of STB.
Internal Register Definition
Table 5 summarises the internal register content. The
first 5 addresses in the table are used to program setup
registers and to provide a software reset feature ( 00H
is reserved). The remaining 3 entries in the table define
the address location of internal data registers. In each
case, a further three sub-addresses are defined for the
red, green and blue register. Selection between the red,
green and blue registers is performed by address bits
a1 and a0, as defined in the table. Setting both a1 and
a0 equal to 1 forces all three registers to be updated to
the same data value. Blank entries in Table 5 should be
programmed to zero.
Figure 16 Serial Interface Timing
SCK
SEN
SDI
a5
a4
Address
a3 a2 a1 a0 b7
WM8143-12
PD. Rev 4 Nov. 99
Data Word