MAX517 Maxim, MAX517 Datasheet - Page 8

• Manufacturer Part Number: MAX517
• Description: 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs
• Manufacturer: Maxim

2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
Figure 2. Two-Wire Serial Interface Timing Diagram
Figure 3. MAX517/MAX518/MAX519 Application Circuit
8
R
1k
SDA
SCL
C
SDA
_______________________________________________________________________________________
t
C
HD
START CONDITION
SCL
,
STA
+5V
SCL
SDA
AD0
AD1
AD2
AD3
SCL
SDA
AD0
AD1
SCL
SDA
AD0
AD1
t
LOW
MAX517
MAX518
SINGLE
MAX519
DUAL
DAC
DAC
DUAL
DAC
t
R
t
SU
t
HIGH
OUT0
OUT1
OUT0
OUT1
OUT0
REF0
REF1
REF0
,
DAT
t
F
+4V
OFFSET ADJUSTMENT
GAIN ADJUSTMENT
BRIGHTNESS ADJUSTMENT
CONTRAST ADJUSTMENT
+1V
+2.5V
THRESHOLD ADJUSTMENT
t
HD
,
DAT
t
SU
REPEATED START CONDITION
,
STA
The address byte and pairs of command and output
bytes are transmitted between the START and STOP con-
ditions. The SDA state is allowed to change only while
SCL is low, with the exception of START and STOP condi-
tions. SDA’s state is sampled, and therefore must remain
stable while SCL is high. Data is transmitted in 8-bit
bytes. Nine clock cycles are required to transfer the data
bits to the MAX517/MAX518/MAX519. Set SDA low dur-
ing the 9th clock cycle as the MAX517/MAX518/MAX519
pull SDA low during this time. R
current that flows during this time if SDA stays high for
short periods of time.
When the bus is not in use, both SCL and SDA must be
high. A bus master signals the beginning of a transmis-
sion with a START condition by transitioning SDA from
high to low while SCL is high (Figure 5). When the mas-
ter has finished communicating with the slave, it issues
a STOP condition by transitioning SDA from low to high
while SCL is high. The bus is then free for another
transmission.
The MAX517/MAX518/MAX519 each have a 7-bit long
slave address (Figure 6). The first three bits (MSBs) of
the slave address have been factory programmed and
are always 010. In addition, the MAX517 and MAX518
have the next two bits factory programmed to 1s. The
logic state of the address inputs (AD0 and AD1 on the
MAX517/MAX518; AD0, AD1, AD2, and AD3 on the
MAX519) determine the LSB bits of the 7-bit slave
address. These input pins may be connected to VDD or
DGND, or they may be actively driven by TTL or CMOS
logic levels. The MAX517/MAX518 have four possible
slave addresses and therefore a maximum of four of
t
HD
,
STA
The START and STOP Conditions
t
SU
,
STO
STOP CONDITION
C
(see Figure 3) limits the
The Slave Address
t
BUF
START CONDITION