MAX5195 Maxim Integrated Products, MAX5195 Datasheet - Page 11

• Manufacturer Part Number: MAX5195
• Description: 260Msps High-Dynamic Performance DAC
• Manufacturer: Maxim Integrated Products

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Table 2. LVPECL Voltage Levels
**V
common-mode level to 2V, allowing a typical peak-to-peak signal swing of 0.8V.
The MAX5195 digital interface consists of 14 differen-
tial, LVPECL-compatible digital input pins. These inputs
follow standard positive binary coding where D0P and
D0N represent the differential inputs to the least signifi-
cant bit (LSB), and D13P and D13N represent the dif-
ferential pair associated with the most significant bit
(MSB). D0P/N through D13P/N accept LVPECL input
levels of 0.8V
Each of the digital input terminals can be terminated
with a separate 50Ω resistor; however, to achieve the
lowest noise performance, it is recommended to termi-
nate each differential pair with a 100Ω resistor located
between the positive and negative input terminals.
The MAX5195 features differential, LVPECL-compatible
clock inputs. Internal edge-triggered flip-flops latch the
input word on the rising edge of the clock-input pair
CLKP/CLKN. The DAC is updated with the data word
on the next rising edge of the clock input. This results in
a conversion latency of one clock cycle. The MAX5195
Figure 4. Input/Output Timing Information
Input Voltage High
Input Voltage Low
Common-Mode Level
CC
is the supply voltage associated with the LVPECL source. A typical V
Clock Inputs (CLKP, CLKN) and Data
LVPECL-Compatible Digital Inputs
PARAMETER
P-P
D13–D0
(Table 2).
CLKN
CLKP
______________________________________________________________________________________
(D0P–D13P, D0N–D13N)
Timing Relationship
MAX5195
MINIMUM LVPECL SPECIFICATION
14-Bit, 260Msps High-Dynamic
t
CH
OUTN
OUTP
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t
SETUP
V
V
CC
CC
t
CL
** - 1.16V
** - 1.81V
provides for minimum setup and hold times (<2ns), allow-
ing for noncritical external interface timing (Figure 4).
For best AC performance, a differential, DC-coupled
clock signal with LVPECL-compatible voltage levels
(Table 2) should be used. The MAX5195 operates
properly with a clock duty cycle set within the limits list-
ed in the Electrical Characteristics table. However, a
50% duty cycle should be utilized for optimum dynamic
performance. To maintain the DAC’s excellent dynamic
performance, clock and data signals should originate
from separate signal sources.
The MAX5195’s current array is designed to drive full-
scale currents of 10mA to 20mA into an internal R2R
resistor network (R
ential output voltage range of 0.5V
OUTP and OUTN should be externally terminated into
27.4Ω (R
25Ω (Figure 5):
t
HOLD
CC
R
R
R
level associated with LVPECL is 3.3V, which sets the
LOAD
LOAD
LOAD
10% POINT
T
), resulting in a combined load of R
V
Performance DAC
CC
= R
= (285Ω
= 25Ω
t
PD
** - 1.3V
Analog Outputs (OUTP, OUTN)
R2R
t
R2R
RISE
MAXIMUM LVPECL SPECIFICATION
, t
|| R
FALL
). To achieve the desired differ-
✕
27.4Ω) / (285Ω + 27.4Ω)
T
90% POINT
V
V
CC
CC
** - 0.88V
** - 1.48V
P-P
to 1V
P-P
LOAD
, both
11
=