MAX536 Maxim, MAX536 Datasheet - Page 12

• Manufacturer Part Number: MAX536
• Description: Calibrated / Quad / 12-Bit Voltage-Output DACs with Serial Interface
• Manufacturer: Maxim

The MAX536/MAX537 contain four 12-bit voltage-output
DACs that are easily addressed using a simple 3-wire
serial interface. They include a 16-bit data-in/data-out
shift register, and each DAC has a double-buffered
input composed of an input register and a DAC register
(see the Functional Diagram on the front page).
The DACs are “inverted” R-2R ladder networks that
convert 12-bit digital inputs into equivalent analog out-
put voltages in proportion to the applied reference-volt-
age inputs. DAC A and DAC B share the REFAB refer-
ence input, while DAC C and DAC D share the REFCD
reference input. The two reference inputs allow different
full-scale output voltage ranges for each pair of DACs.
Figure 1 shows a simplified circuit diagram of one of
the four DACs.
The two reference inputs accept positive DC and AC
signals. The voltage at each reference input sets
the full-scale output voltage for its two correspond-
ing DACs. The REFAB/REFCD voltage range is 0V to
(V
MAX537. The output voltages V
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
12
_______________Detailed Description
______________________________________________________________Pin Description
DD
PIN
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
______________________________________________________________________________________
- 4V) for the MAX536 and 0V to (V
REFCD
REFAB
NAME
DGND
AGND
OUTD
OUTC
OUTB
OUTA
LDAC
SDO
SCK
V
V
SDI
CS
TP
DD
SS
DAC B Output Voltage
DAC A Output Voltage
Negative Power Supply
Analog Ground
Reference Voltage Input for DAC A and DAC B
Digital Ground
Load DAC Input (active low). Driving this asynchronous input low transfers the contents of all input
registers to their respective DAC registers.
Serial Data Input. Data is shifted into an internal 16-bit shift register on SCK's rising edge.
Chip-Select Input (active low). A low level on CS enables the input shift register and SDO.
On CS’s rising edge, data is latched into the appropriate register(s).
Shift Register Clock Input
Serial Data Output. SDO is the output of the internal shift register. SDO is enabled when CS is low.
For the MAX536, SDO is an open-drain output. For the MAX537, SDO has an active pull-up to V
Reference Voltage Input for DAC C and DAC D
Test Pin. Connect to V
Positive Power Supply
DAC D Output Voltage
DAC C Output Voltage
OUT
Reference Inputs
_ are represented by
DD
- 2.2V) for the
DD
for proper operation.
a digitally programmable voltage source as:
where N
code (0 to 4095) and V
Figure 1. Simplified DAC Circuit Diagram
SHOWN FOR ALL 1s ON DAC
AGND
REF
FUNCTION
B
2R
is the numeric value of the DAC’s binary input
D0
2R
V
R
OUT_
= N
REF
2R
D9
B
R
is the reference voltage.
(V
REF)
2R
D10
R
/ 4096
2R
D11
DD
.
V
OUT