MAX555 Maxim, MAX555 Datasheet - Page 5

• Manufacturer Part Number: MAX555
• Description: 300Msps / 12-Bit DAC with Complementary Voltage Outputs
• Manufacturer: Maxim

_____________________Pin Description
10, 11, 12,
21–25, 27,
31, 36, 37,
40, 41, 43,
19, 49, 51,
20, 29, 30,
54, 58, 59,
60, 62, 64,
45, 46, 61
52, 53, 68
4, 56, 57,
65, 67, 6,
63, 66
13, 14
15, 16
17, 18
26, 44
33, 34
38, 39
7, 8, 9
5, 55
PIN
48
28
32
35
42
47
50
1
2
3
ALTCOMPIB
LOOPCRNT
ALTCOMPC
D11(MSB)–
ROFFSET
BYPASS
D0(LSB)
VREF/2
NAME
DGND
AGND
LGND
LBIAS
VOUT
VOUT
VREF
DV
AV
N.C.
CLK
CLK
TN
HS
_______________________________________________________________________________________
EE
EE
Disables latching of data
when high (ECL input)
Data Clock (ECL input)
Data Clock Not (ECL input)
Digital Signal Grounds
-5.2V Digital Power Supplies
No Connection
DAC Outputs
Ladder Grounds
DAC Output Complements
Test Node—internal test point,
do not connect
Analog Signal Grounds
Heatspreader Connections—
bypass with 0.1µF to AV
PTAT-IB Reference
Compensation Output (con-
nect bypass capacitor to
AV
Test node—must connect to
AGND
-5.2V Analog Power Supplies
Analog Reference Voltage
Center-Tap Input
Analog Reference Voltage
Inputs (Kelvin connection)
Offset Compensation Input
Control-Amplifier PTAT
Reference Compensation
Input (connect bypass capaci-
tor to AV
Ladder-Bias Alternate
Compensation Output (con-
nect bypass capacitor to AV
Data Words (ECL inputs)
EE
)
EE
FUNCTION
Complementary Voltage Outputs
)
EE
EE
300Msps, 12-Bit DAC with
)
Figure 1’s functional diagram shows the MAX555’s three
major divisions: a digital section, a control-amplifier sec-
tion, and a resistor-divider network. The digital section
consists of a master/slave register, decoding logic, and
current switches. The control-amplifier section includes a
control amplifier and an array of 23 current sources divid-
ed into three groups. The resistor divider scales the cur-
rents from these groups to achieve the correct binary
weighting at the output. The output of the resistor-divider
network is laser trimmed to 50Ω, a key feature for driving
into controlled impedance transmission lines.
The first group of current sources comprises the six
MSBs, D11–D6 (resulting in 15 identical, plus two binary
weighted currents), which are applied directly to the out-
put of the resistor-divider network. The second group,
bits D5–D3 (three binary weighted currents), is applied
to the middle of the divider network. The middle of the
network divides the current seen at the output by 8. The
third group, bits D2–D0 (three additional binary weighted
current sources), is applied to the input of the resistive
network, dividing the current seen at the output by 64.
Glitching is reduced by decoding the four MSBs into 15
identical current sources and synchronizing data with a
master/slave register at every current switch. Data bits
are transferred to the output on the positive-going edge
of the clock, with the BYPASS input asserted low. In
the asynchronous mode with the BYPASS input assert-
ed high, the latches are transparent and data is trans-
ferred to the output regardless of the clock state. All
digital inputs are ECL compatible. The clock input is
differential.
The control amplifier forces a reference current, which is
replicated in the current sources. This reference current
is nominally 1.25mA. It can be supplied by an external
current source, or by an external voltage source of
1.000V applied to the VREF input.
A reference input of V
scale output voltage of V
for the VOUT output. The output coding is summarized
in Table 1.
The DAC’s control amplifier has a typical open-loop volt-
age gain of 85dB, and its gain-magnitude bandwidth is
flat up to 10MHz. When the control amplifier is not being
used for high-speed multiplying applications, it is recom-
mended that a 0.4µF capacitor be connected from LBIAS
to AV
current-source noise.
_______________Detailed Description
EE
to increase control-amplifier stability and reduce
V
FS
= 4096 / 4095 x VOUT (code 0)
REF
FS
= 1.000V will produce a full-
= -1.000V, where:
5