AT945 ATMEL Corporation, AT945 Datasheet - Page 12
AT945
Manufacturer Part Number
AT945
Description
Secure 5K - 40K Gates of At40k FPGA with 8-bit Microcontroller,up to 36 Kbytes of SRAM and On-chip Program Storage Eeprom
Manufacturer
ATMEL Corporation
Datasheet
1.AT945.pdf
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12
AT94S Secure Family
Figure 3. Typical System Setup
The diode connection between the AT94S’ RESET pin and the SER_EN signal allows
the external programmer to force the FPGA into a reset state during ISP. This eliminates
the potential for contention on the cSCK line. The pull-up resistors required on the lines
to RESET, CON and INIT are present on the inputs (internally) to the AT94S FPSLIC,
see Figure 4.
Figure 4. ISP of the AT17LV512/010 in an AT94S FPSLIC Application
Note:
RESET
1. Configurator signal names are shown in parenthesis.
GND
PC
RESET
M2
M0
ATDH2225
INIT (RESET/OE)
Programming
DATA0 (cSDA)
AT94S
Dongle
CLK (cSCK)
CON (CE)
(SER_EN)
Ribbon
10-pin
Cable
(1)
(1)
(1)
(1)
10
Programming
Connector
In-System
Header
FPSLIC
Secure
Target System
GND
FPSLIC
Secure
cSDA
cSCK
1
3
5
7
9
2314D–FPSLI–2/04
SER_EN
2
4
6
8
10
V
CC
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