ADC700JH Burr-Brown Corporation, ADC700JH Datasheet - Page 6

• Manufacturer Part Number: ADC700JH
• Description: 16-bit Resolution With Microprocessor Interface A/D Converter
• Manufacturer: Burr-Brown Corporation

TWO’S COMPLEMENT DATA CODE
BTCEN (pin 23) is a logic function that implements the
Binary Two’s Complement output code for bipolar (+ and –)
analog input signal operation. This feature is compatible
with twos complement arithmetic in microprocessor math
algorithms.
INTERNAL CLOCK
The ADC700 has a self-contained clock to sequence the
A/D logic. The clock is not available externally. An external
16-pulse strobe (pin 14) is brought out to clock serial data
only. Use of ADC700 with external clock is not possible.
INTERNAL VOLTAGE REFERENCE
The ADC700 has an internal low-noise buried-zener voltage
reference. The reference circuit has been drift compensated
over the MIL temperature range using a laser trim algorithm.
The reference voltage is not available externally.
DISCUSSION
OF SPECIFICATIONS
BASIC DEFINITIONS
Refer to Figure 3 for an illustration of A/D converter
terminology and to Table II in the Calibration section.
Full Scale Range, FSR
The nominal range of the A/D converter. For ADC700, the
FSR is 20V for the 0V to +20V and the –10V to +10V input
ranges or 10V for the 0V to +10V and –5V to +5V input
ranges.
Least Significant Bit, LSB
The smallest analog input change resolved by the A/D
converter. For an A/D converter with N bits output, the input
value of the LSB is FSR(2
FIGURE 1. Load Circuits for Access Time.
FIGURE 2. Load Circuits for Output Float Delay.
DBN
DBN
A) High-Z to V
and V
A) V
3k
OH
OL
®
DGND
3k
DGND
to High-Z.
to V
ADC700
OH
OH
(t
3
(t
)
6
C
10pF
).
L
–N
).
B) High-Z to V
DBN
DBN
and V
B) V
OL
OH
to High-Z.
to V
5V
3k
DGND
OL
C
5V
3k
DGND
OL
10pF
L
(t
(t
3
)
6
).
6
Most Significant Bit, MSB
That binary digit that has the greatest value or weight. The
MSB weight is FSR/2.
Resolution
An N-bit binary-coded A/D converter resolves the analog
input into 2
codes.
ACCURACY
Linearity Error, Integral Linearity Error (ILE)
Linearity Error is defined as the deviation of actual analog
input values from the ideal values about a straight line drawn
through the code mid-points near positive full scale (at +V
–1LSB) and at Zero input (at 1/2LSB below the first code
transition, i.e. at Zero) or, in the case of bipolar operation,
near minus full scale (at 1/2LSB below the first code
transition, i.e. at –V
code transitions are easier to measure than code midpoints.
Therefore linearity is measured as the deviation of the
analog input values from a line drawn between the first and
last code transitions. Linearity Error specifications are ex-
pressed in % of Full Scale Range (FSR). ADC700KH ILE
is 0.003% of FSR which is 1/2 LSB at 14-bits.
Differential Linearity Error (DLE), No Missing Codes
Differential Linearity Error is defined as the deviation in
code width from the ideal value of 1LSB. If the DLE is
greater than –1LSB anywhere along the range, the A/D will
have at least one missing code. ADC700KH is specified to
have a DLE of 0.006% of FSR, which is 1LSB at 14 bits.
ADC700KH is specified to have no missing codes at the 14-
bit level over specified temperature ranges.
Gain Error
The deviation from the ideal magnitude of the input span
between the first code midpoint (at –V
bipolar operation; at Zero for unipolar operation) to the last
code midpoint (V
FIGURE 3. Transfer Characteristic Terminology.
FFD
FFF
FFE
7FE
7FF
802
801
800
002
001
000
H
H
H
H
H
H
H
H
H
H
H
1/2LSB
Scale)
(–Full
Zero
N
Offset Error
Shifts The Line
values represented by the 2
(–Full-Scale
Calibration
Transition)
FS
Zero
FS
–1LSB). As with the linearity error
Transition)
). Despite the definition, however,
(Bipolar
Zero
Analog Input
1/2LSB
Gain
Error
Rotates
The
Line
Midscale
(Bipolar Zero)
+Full-Scale
Calibration
3/2LSB
FS
Transition
N
+ 1/2LSB, for
digital output
+Full
Scale
FS