MAX6975 Maxim Integrated Products, MAX6975 Datasheet - Page 19

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MAX6975

Manufacturer Part Number
MAX6975
Description
(MAX6974 / MAX6975) 24-Output PWM LED Drivers
Manufacturer
Maxim Integrated Products
Datasheet

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The MAX6974/MAX6975 serial-interface protocol timing
is simplified by the guaranteed setup and hold charac-
teristics of the outputs from one device driving the
inputs of another. An example of a cascade of three
MAX6974/MAX6975 devices is shown in
The basic timing of a MAX6974/MAX6975 cascaded
chain of three devices demonstrates the principle that
applies to any number of cascaded devices. The first
device connected to the host transmitter is referenced
as 1, and the remaining devices are referenced as 2
and 3. Device 3 outputs connect to the host for commu-
nicating diagnostic and fault counter data.
The first MAX6974/MAX6975, device 1, receives the
header and captures the first set of data bits. The
number of captured bits is determined by the command
given in the header. A timing example of the data trans-
fer for the Load CALDAC command is shown in Figure
9. Device 1 does not send the captured data out on
DOUT. Instead, device 1 sends out a new header 25
clock cycles after the reception of the first header bit on
DIN. The data flow on each interconnect node is shown
in
Figure 8. Example Showing Three-Device Cascade Connection Scheme with the Interconnecting Nodes Labeled for Clarity
Figure 9. Timing Example Showing CALDAC Data Set for the First Two Cascaded Devices
(CONTINUOUS)
Figure
LOADI
CLKI
DIN
1
0
10.
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
HOST
LOADO
LOADI
CLKO
DOUT
CLKI
DIN
Serial-Interface Cascade Timing
B CALDAC
______________________________________________________________________________________
Example of Serial-Interface
LOAD0
CLK0
D0
CLKI
DIN
LOADI
DATA: CALDAC DATA 1
MAX6974/MAX6975
G CALDAC
Cascade Timing
1
LOADO
DOUT
CLKO
Figure
LOAD1
CLK1
D1
8.
24-Output PWM LED Drivers
G CALDAC
CLKI
DIN
LOADI
MAX6974/MAX6975
After capturing the first data set, device 1 transmits all
following data segments and the optional tail segment
on DOUT, delayed by one CLKI cycle. Device 2
receives the new header from device 1, followed by
data that now begins with device 2’s data set. Device 2
repeats the same process as described above; captur-
ing the first data set received, appending a new head-
er, and passing all subsequent data out DOUT to the
next device 3. Device 3 captures the last data set and
transmits a header followed by the tail segment. The
last header and tail segments are clocked back into the
host receiver. The header received by the host contains
the updated fault counter data. The tail data bit pattern
can be compared to the tail data originally transmitted
by the host for data integrity check.
Figure 10. Data Cascading Example for 24-Bit Data Words
2
D0
D1
D2
D3
CLK0
LOADO
DOUT
CLKO
B CALDAC
for Message Boards
25 CLOCKS
HEADER 1
LOAD2
CLK2
D2
CLKI
DIN
LOADI
MAX6974/MAX6975
DATA: CALDAC DATA 2
HEADER 2
25 CLOCKS
3 BYTES 1
G CALDAC
3
LOADO
DOUT
CLKO
HEADER 3
3 BYTES 2
25 CLOCKS
3 BYTES 2
LOAD3
CLK3
D3
R CALDAC
3 BYTES 3
3 BYTES 3
3 BYTES 3
HEADER 4
T
T
T
T
IDLE
IDLE
IDLE
IDLE
19

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