MAX8649 Maxim Integrated Products, MAX8649 Datasheet - Page 17

• Manufacturer Part Number: MAX8649
• Description: 1.8A Step-Down Regulator
• Manufacturer: Maxim Integrated Products

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A START condition from the master signals the begin-
ning of a transmission to the MAX8649. The master ter-
minates transmission by issuing a not acknowledge
followed by a STOP condition (see the Acknowledge
section for more information). The STOP condition frees
the bus. To issue a series of commands to the slave,
the master can issue REPEATED START (Sr) com-
mands instead of a STOP command to maintain control
of the bus. In general, a REPEATED START command
is functionally equivalent to a regular START command.
When a STOP condition or incorrect address is detect-
ed, the MAX8649 internally disconnects SCL from the
serial interface until the next START condition, minimiz-
ing digital noise and feedthrough.
A device on the I
called a transmitter and a device that receives the mes-
sage is a receiver. The device that controls the mes-
sage is the master and the devices that are controlled
by the master are called slaves. See Figure 11.
The number of data bytes between the START and
STOP conditions for the transmitter and receiver are
unlimited. Each 8-bit byte is followed by an acknowl-
edge bit. The acknowledge bit is a high-level signal put
on SDA by the transmitter during which time the master
generates an extra acknowledge-related clock pulse. A
slave receiver that is addressed must generate an
acknowledge after each byte it receives. Also, a master
receiver must generate an acknowledge after each
byte it receives that has been clocked out of the slave
transmitter. See Figure 12.
Figure 11. I
2
CMaster/Slave Configuration
1.8A Step-Down Regulator with Differential
SDA
SCL
2
______________________________________________________________________________________
C bus that generates a message is
TRANSMITTER/RECEIVER
MASTER
Remote Sense in 2mm x 2mm WLP
System Configuration
Acknowledge
SLAVE RECEIVER
The device that acknowledges must pull down the
DATA line during the acknowledge clock pulse, so that
the DATA line is stable low during the high period of the
acknowledge clock pulse (setup and hold times must
also be met). A master receiver must signal an end of
data to the transmitter by not generating an acknowl-
edge on the last byte that has been clocked out of the
slave. In this case, the transmitter must leave SDA high
to enable the master to generate a STOP (P) condition.
The I
the voltage at either IN1 or V
corresponding UVLO threshold (see the Electrical
Characteristics table).
Figure 12. I
FROM TRANSMITTER
FROM RECEIVER
2
C resisters reset back to their default values when
SDA OUTPUT
SDA OUTPUT
SCL FROM
MASTER
2
C Acknowledge
START CONDITION
TRANSMITTER/RECEIVER
D7
1
SLAVE
D6
2
NOT ACKNOWLEDGE
ACKNOWLEDGE
DD
drops below the
Register Reset
ACKNOWLEDGEMENT
CLOCK PULSE FOR
D0
8
9
17