MAX9526 Maxim Integrated Products, MAX9526 Datasheet - Page 9

• Manufacturer Part Number: MAX9526
• Description: High-Performance NTSC/PAL Video Decoder
• Manufacturer: Maxim Integrated Products

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15–20, 25–28
QSOP
10, 22
11, 23
12
13
14
21
24
—
—
1
2
3
4
5
6
7
8
9
PIN
9, 17, 25, 29
19, 24, 26,
13–16, 18,
TQFN-EP
27, 28
_______________________________________________________________________________________
7, 21
8, 22
30
31
32
10
11
12
20
23
—
1
2
3
4
5
6
XTAL/OSC
DEVADR
DVDDIO
D0–D9
NAME
AGND
XTAL2
DGND
DVDD
AVDD
V
SDA
N.C.
V
V
SCL
IRQ
LLC
I.C.
EP
REF
IN1
IN2
Single-Ended Composite Video Input 1. AC-couple the input video signal with a 0.1µF
capacitor.
Video Reference Bypass. Bypass V
possible to the device.
Single-Ended Composite Video Input 2. AC-couple the input video signal with a 0.1µF
capacitor.
Analog Ground
Analog Power-Supply Input. Connect to a +1.8V supply. Bypass AVDD to AGND with a
0.1µF capacitor.
External Crystal. Connect XTAL2 to one terminal of the crystal oscillator. Ground XTAL2
when applying an external clock to XTAL/OSC.
External Crystal/Oscillator. Connect XTAL/OSC to one terminal of a crystal or an
external clock source. Connect XTAL2 to the other terminal of the crystal oscillator.
Internal connection. Connect to DGND.
I
available I
Digital Power-Supply Input. Connect to a +1.8V supply. Bypass DVDD to DGND with a
0.1µF capacitor in parallel with a 10µF capacitor.
Digital Ground. Connect both DGND terminals together.
I
DVDDIO for full output swing.
I
DVDDIO for full output swing.
Hardware Interrupt Open-Drain Output. If not masked, IRQ is pulled low when the bits
in the status register change state. Repeated faults have no effect on IRQ until IRQ is
cleared by reading the corresponding status register. Connect a 10kΩ pullup resistor
from IRQ to DVDDIO for full output swing.
Digital Video Outputs Bit 0–Bit 9, 10-Bit Component Digital Video Outputs. The output
format is 10-bit ITU-R BT.656, 4:2:2 with embedded sync. D1 and D0 can be
configured as horizontal and vertical sync outputs using the Clock and Output register
0x0D. D0 is LSB.
Line-Locked 27MHz Clock Output. With line-locked mode, the LLC clock varies in
response to horizontal line rate of the incoming video. In async mode, the LLC clock is
synchronous to the crystal (see Table 1).
Digital I/O Power-Supply Input. Accepts a +1.7V to +3.45V voltage input. Bypass to
DGND with a 0.1µF capacitor.
No Connection. Not internally connected.
Exposed Pad. EP is internally connected to GND. Connect EP to GND.
2
2
2
C-Compatible Serial-Clock Input. Connect a 10kΩ pullup resistor from SCL to
C Device Address Select Input. Connect to DVDD, DGND, or SDA to select 1 of 3
C-Compatible Serial-Data Input/Output. Connect a 10kΩ pullup resistor from SDA to
Low-Power, High-Performance
2
C slave addresses (see Table 5).
NTSC/PAL Video Decoder
REF
FUNCTION
to AGND with a 0.1µF capacitor as close as
Pin Description
9