MAX9853 Maxim Integrated Products, MAX9853 Datasheet - Page 29

• Manufacturer Part Number: MAX9853
• Description: (MAX9851 / MAX9853) Stereo Audio CODECs
• Manufacturer: Maxim Integrated Products

The MAX9851 CODEC, with a stereo DirectDrive head-
phone amplifier and a stereo Class D speaker amplifi-
er, is a complete digital audio solution for GSM/
GPRS/EDGE cell phones and PDA phones. The
MAX9853 audio CODEC shares all the functionality of
the MAX9851 without the Class D speaker amplifier,
substituting it with stereo differential line outputs to
facilitate external amplifiers and other analog audio
devices. The MAX9851/MAX9853 additionally feature
stereo and mono microphone inputs, and a mono
DirectDrive handset receiver amplifier combined with
sigma-delta stereo DACs and stereo ADCs.
The sigma-delta DAC has 88dB of dynamic range and
accepts stereo audio data from two independent digital
audio interfaces at sampling frequencies ranging from
8kHz to 48kHz. The interfaces can accept I
ble data in addition to voiceband data and allows the
mixing of multiple audio sources at different unrelated
sample rates. The primary digital audio input integrates
bandpass filtering that can be used when operating in
voice mode. Digital audio from the ADC can output on
both interfaces allowing maximum flexibility.
Analog and digital volume levels, muting, and device
configuration are programmed through the I
ible interface. Audio data is sent to and from the
MAX9851/MAX9853 through either of two 4-wire digital
audio data buses that support numerous formats.
LRCLK and BCLK signals are generated by the
MAX9851/MAX9853 when configured in master mode.
The MAX9851/MAX9853 can also be configured as a
slave DAC stereo audio playback device or a full
duplex slave voice CODEC, accepting LRCLK and
BCLK signals from an external digital audio master.
Maxim’s patented DirectDrive architecture employs an
internal charge pump to create a negative voltage sup-
ply powering the headphone and receiver amplifier out-
puts. The internal negative supply allows the analog
output signals to be biased at ground, eliminating the
need for an output-coupling capacitor, reducing sys-
tem cost and size. The MAX9851/MAX9853’s stereo
line inputs allow mixing of analog audio with digital
audio. Numerous signal routing options and program-
mable gain allow any combination of analog and digital
input signals at varying signal levels to be routed to any
output. Sophisticated headset sensing circuitry allows
Stereo Audio CODECs with Microphone, DirectDrive
Headphones, Speaker Amplifiers, or Line Outputs
______________________________________________________________________________________
Detailed Description
2
2
S-compati-
C-compat-
the MAX9851/MAX9853 to detect a wide variety of
headset configurations and trigger a hardware interrupt
on jack insertion (even when powered down). The
external stereo microphone inputs provide configurable
internal bias resistors and a gain range of 40dB to
accommodate a wide variety of microphones. The
internal mono microphone input provides a differential
input and a gain range of 40dB. The VIBE digital output
can be used to control a vibrator, transducer, or can be
used as a general-purpose digital output.
The MAX9851/MAX9853 have two independent digital
audio interfaces, S1 and S2, each capable of operating
independently in the full-duplex master and slave tim-
ing modes shown in Figures 1 and 2. The second digi-
tal audio interface operates from a secondary supply
voltage (DV
ple supply systems.
Set S1SDO or S2SDO to 1 (register 0x03 or 0x05, bit
B7) to enable the output of ADC data to the corre-
sponding SDOUT pin. Enabling both SDOUTS1 and
SDOUTS2 will output the same digital audio signal on
both interfaces and the primary S1 interface will specify
the sample rate of the ADC.
Set S1SDI or S2SDI to 1 (register 0x03 or 0x05, bit B6)
to enable DAC input and begin an internal soft-start
sequence for the corresponding SDIN pin. Clearing a
particular SDI bit begins an internal soft-stop sequence
prior to disabling the input. The SLD slew detect status
bit (register 0x00, bit B6) indicates when a soft-
start/stop sequence has completed. This allows inter-
face mode changes without interrupting the other
interface’s signal flow. Clear both S1SDI and S2SDI
before enabling the left and right DAC with DACLEN
and DACREN (register 0x1B, bits B7 and B6).
To achieve the most exact sample clocks, operate the
MAX9851/MAX9853 in slave mode with the exact
LRCLK provided externally (in DAC-only mode) or in
master mode with the ADCs disabled. The ADC
requires an exact integer LRCLK frequency resulting in
less accurate sample clocks than when only operating
the DAC. Slave mode is only available for the DACs
when the ADCs are inactive, or for fully synchronous
8kHz and 16kHz voice modes.
Table 1 lists the MAX9851/MAX9853 available interface
modes for each sampling frequency.
DDS2
) to allow simple integration into multi-
Serial Digital Audio Interface
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