ADS1255IDB Burr-Brown Corporation, ADS1255IDB Datasheet - Page 16

• Manufacturer Part Number: ADS1255IDB
• Description: Very Low Noise/ 24-Bit Analog-to-Digital Converter
• Manufacturer: Burr-Brown Corporation

ADS1255
ADS1256
SBAS288D − JUNE 2003 − REVISED AUGUST 2004
PROGRAMMABLE GAIN AMPLIFIER (PGA)
The ADS1255/6 is a very high resolution converter. To
further complement its performance, the low-noise PGA
provides even more resolution when measuring smaller
input signals. For the best resolution, set the PGA to the
highest possible setting. This will depend on the largest
input signal to be measured. The ADS1255/6 full-scale
input voltage equals
full-scale input voltage for the different PGA settings for
V
measured is 1.0V, the optimum PGA setting would be 4,
which gives a full-scale input voltage of 1.25V. Higher
PGAs cannot be used since they cannot handle a 1.0V
input signal.
The PGA is controlled by the ADCON register.
Recalibrating the A/D converter after changing the PGA
setting
self-calibration is dependent on the PGA setting. See the
Calibration section for more details. The analog current
and input impedance (when the buffer is disabled) vary as
a function of PGA setting.
MODULATOR INPUT CIRCUITRY
The ADS1255/6 modulator measures the input signal
using internal capacitors that are continuously charged
and discharged. Figure 9 shows a simplified schematic of
the ADS1255/6 input circuitry with the input buffer
disabled. Figure 10 shows the on/off timings of the
switches of Figure 9. S1 switches close during the input
sampling phase. With S1 closed, C
charges to AIN
discharge phase, S1 opens first and then S2 closes. C
and C
discharges to 0V. This two-phase sample/discharge cycle
16
PGA SETTING FULL-SCALE INPUT VOLTAGE (V REF = 2.5V)
REF
= 2.5V. For example, if the largest signal to be
16
32
64
A2
1
2
4
8
Table 8. Full-Scale Input Voltage vs
is
discharge to approximately AVDD/2 and C
recommended.
N
, and C
PGA Setting
B
2V
charges to (AIN
REF
/PGA. Table 8 shows the
The time required for
156.25mV
78.125mV
312.5mV
0.625V
1.25V
A1
2.5V
5V
charges to AIN
P
– AIN
N
). For the
P
, C
A2
A1
B
repeats with a period of
the PGA setting as shown in Table 9 along with the values
of the capacitor C
SETTING
(1) SAMPLE for f CLKIN = 7.68MHz.
Figure 10. S1 and S2 Switch Timing for Figure 9
S
S
PGA
1
2
Table 9. Input Sampling Time,
16
32
64
1
2
4
8
OFF
OFF
ON
ON
AINCOM
Figure 9. Simplified Input Structure
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
f CLKIN /4 (521ns)
f CLKIN /4 (521ns)
f CLKIN /4 (521ns)
f CLKIN /4 (521ns)
f CLKIN /4 (521ns)
f CLKIN /2 (260ns)
f CLKIN /2 (260ns)
SAMPLE (1)
A1
C
A
with Buffer Off
Multiplexer
= C
and C
Input
SAMPLE
A2
SAMPLE
= C
B
AIN P
AIN N
A
vs PGA
. This time is a function of
and C
S1
S1
S2
S2
2.1pF
4.2pF
8.3pF
17pF
33pF
33pF
33pF
AVDD/2
AVDD/2
C A
B
SAMPLE
.
www.ti.com
C A1
C A2
C B
, and
2.4pF
4.9pF
9.7pF
19pF
39pF
39pF
39pF
C B