ADS7810 Burr-Brown Corporation, ADS7810 Datasheet - Page 8

• Manufacturer Part Number: ADS7810
• Description: 12-Bit 800kHz Sampling CMOS ANALOG-to-DIGITAL CONVERTER
• Manufacturer: Burr-Brown Corporation

To reduce the number of control pins, CS can be tied LOW
using R/C to control the read and convert modes. Note that
the parallel output will be active whenever R/C is HIGH and
no conversion is in progress. See the Reading Data section
and refer to Table I for control line functions for ‘read’ and
‘convert’ modes.
READING DATA
The ADS7810 outputs full parallel data in Binary Two’s
Complement data format. The parallel output will be active
when R/C (pin 23) is HIGH, CS (pin 24) is LOW, and no
conversion is in progress. Any other combination will tri-
state the parallel output. Valid conversion data can be read
in a full parallel, 12-bit word on D11-D0 (pins 6-13 and 15-
18). Refer to Table II for ideal output codes.
After the conversion is completed and the output registers
have been updated, BUSY (pin 25) will go HIGH. Valid data
from the most recent conversion will be available on
D11-D0 (pins 6-13 and 15-18). BUSY going HIGH can be
used to latch the data. Refer to Table III and Figures 2
and 3.
Note: For the best performance, the external data bus con-
nected to D11-D0 should not be active during a conversion.
The switching noise of the external asynchronous data
signals can cause digital feedthrough degrading the
converter’s performance.
The number of control lines can be reduced by tieing CS
LOW while using R/C to initiate conversions and activate
the output mode of the converter. See Figure 2.
INPUT RANGES
The ADS7810 offers a standard 10V input range. Figures
4a and 4b show the necessary circuit connections for the
ADS7810 with and without external trim. Offset and full
scale error
the 50
makes it possible to trim the offset 50mV using a trim pot
or trim DAC. This resistor may be left out if the offset and
gain errors will be corrected in software or if they are
negligible in regards to the particular application. See the
Calibration section of the data sheet for details.
resistor shown in Figure 4b. This external resistor
(1)
®
specifications are tested and guaranteed with
ADS7810
8
The nominal input impedance of 3.125k
NOTE: (1) Full scale error includes offset and gain errors measured at both
+FS and –FS.
TABLE III. Timing Specifications (T
combination of the internal resistor network shown on the
front page of the product data sheet and external 50
resistor. The input resistor divider network provides inherent
overvoltage protection guaranteed to at least 25V. The
50 , 1% resistor does not compromise the accuracy or drift
of the converter. It has little influence relative to the internal
resistors, and tighter tolerances are not required.
Note: The values shown for the internal resistors are for
reference only. The exact values can vary by 30%. This is
true of all resistors internal to the ADS7810. Each resistive
divider is trimmed so that the proper division is achieved.
SYMBOL
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
7
9
10
11
12
13
& t
8
Bus Relinquish Time
Convert Pulse Width
BUSY Delay After
End of Conversion
Bus Access Time
Data Valid Delay
Conversion Time
Throughput Time
Acquisition Time
After Data Valid
From R/C LOW
DESCRIPTION
After R/C LOW
Aperture Delay
Time Between
BUSY Delay
BUSY Delay
Conversions
BUSY LOW
Setup Time
R/C to CS
1250
MIN
40
20
10
10
10
MIN
1110
TYP
955
950
910
200
70
90
20
50
65
25
to T
results from the
MAX
MAX
1095
1080
1020
1250
125
230
120
83
62
).
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns