ADSP-2103KP-40 Analog Devices, ADSP-2103KP-40 Datasheet - Page 45
ADSP-2103KP-40
Manufacturer Part Number
ADSP-2103KP-40
Description
ADSP-2100 Family DSP Microcomputers
Manufacturer
Analog Devices
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REV. B
TIMING PARAMETERS (ADSP-2103/2162/2164)
CLOCK SIGNALS & RESET
Parameter
Timing Requirement:
t
t
t
t
Switching Characteristic:
t
t
t
NOTES
1
Applies after powerup sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
CK
CKL
CKH
RSP
CPL
CPH
CKOH
oscillator startup time).
CLKIN Period
CLKIN Width Low
CLKIN Width High
RESET Width Low
CLKOUT Width Low
CLKOUT Width High
CLKIN High to CLKOUT High
CLKOUT
CLKIN
Figure 39. Clock Signals
10.24 MHz
Min
97.6
20
20
488
38.8
38.8
0
t
CKL
t
t
CK
CPL
–45–
Max
150
20
t
CKH
t
t
CKOH
CPH
Frequency
Dependency
Min
5t
0.5t
0.5t
CK
CK
CK
1
– 10
– 10
Max
ADSP-21xx
Unit
ns
ns
ns
ns
ns
ns
ns
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