AL4CS241 AverLogic Technologies, Inc., AL4CS241 Datasheet - Page 6

• Manufacturer Part Number: AL4CS241
• Manufacturer: AverLogic Technologies, Inc.

5.0 Pin-out Diagram
The AL4CS211/AL4CS221/AL4CS231/AL4CS241/AL4CS251 pin-out diagram is following:
6.0 Block Diagram
The internal structure of the AL4CS211/AL4CS221/AL4CS231/AL4CS241/AL4CS251 consists of
Input/Output buffers, Read/Write Control Logic and main (512, 1k, 2k, 4k, 8k) x9 different
configuration memory cell array and state-of-the-art logic design that takes care of addressing and
controlling the read/write data.
AL4CS211/AL4CS221/AL4CS231/AL4CS241/AL4CS251
/WEN1
WEN2
WCLK
Input data bus
/LD
/RS
/RS
D8
D7
D6
D5
D4
D3
D2
25
26
27
28
29
30
31
32
TQFP PACKAGE TOP VIEW
Regissers
Offset
Write Control
Write Pointer
Reset Logic
AVERLOGIC
AL4CS2X1
x-xx-xx
xxxx
xxxx
Logic
Buffer
Input
Figure 1. AL4CS2x1 FIFO Block Diagram
16
15
14
13
12
11
10
9
Q4
Q3
Q2
Q1
Q0
/EF
/OE
/FF
(512, 1k ,2k,
4k, 8k) x9
Memory
Array
AL4CS211/AL4CS221/AL4CS231/AL4CS241/AL4CS251
/EF
/FF
Q0
Q1
Q2
Q3
Q4
14
15
16
17
18
19
20
13
21
12
22
11
23
Read Control
Flag Logic
Read Pointer
AVERLOGIC
AL4CS2X1
x-xx-xx
xxxx
xxxx
PLCC PACKAGE TOP VIEW
Output
Buffer
10
24
Logic
9
25
8
26
7
27
Output data bus
6
28
/OE
5
December 14, 2001
29
1
32
31
30
/REN2
/REN1
4
3
2
RCLK
D2
D3
D4
D5
D6
D7
D8
/FF
/EF
/PAF
/PAE
6