SMT4004A Summit Microelectronics, Inc., SMT4004A Datasheet
SMT4004A
Related parts for SMT4004A
SMT4004A Summary of contents
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... The SMT4004A incorporates nonvolatile program- mable circuits for setting all monitored thresholds for each manager. Individual functions are also pro- grammable allowing Interrupts or Reset conditions to be generated by many combinations of events ...
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... DETAILED DEVICE DESCRIPTION SUPPLY MANAGERS The SMT4004A has four distinct programmable power supply managers and associated circuitry (see Figure 7). The managers are individually programmable and can operate independently or together with the other managers. Each manager monitors the bus and card- side voltages and current for that supply (Figure 1). ...
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... RST# (Figure 2), an IRQ#, (Figure internal force shutdown (FSD) and crowbar output (Figure 5). DEVICE POWER SUPPLY The VI inputs also provide the operating supply voltage for the SMT4004A. Internally they are diode- ORed, so the highest potential VI input becomes the VDD supply. Refer to the functional Block Diagram on page 8. ...
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... UV1 3 UV2 UV1 4 UV2 IRQ# SELECT REGISTER QT_CB 4 QT_CB 3 QT_CB 2 QT_CB 1 Figure 3. Interrupt sources from the SMT4004A supply managers. Summit Microelectronics, Inc (CONTINUED IRQ# SELECT REGISTER 2072 1.1 3/7/03 SMT4004A IRQ# SET ...
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... Tracker Select Regs VGATE CONTROL SOFTSTART DONE VGATE CONTROL TRACKING Figure 4. Charge Pump and VGATE Control 2072 1.1 3/7/03 SMT4004A PWR_ON, SEATED1# and Charge Pump VGATE1 VGATE Circuit VGATE2 VGATE Circuit VGATE3 VGATE Circuit VGATE4 VGATE Circuit FSD TRKR 1 ...
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... RST#s, FAULT STATUS REGISTERS The SMT4004A has three nonvolatile fault status registers. When an IRQ# is generated the cause of the interrupt is recorded in the fault register. The fault source is indicated as a ‘1’ in the assigned bit location (Table 1). The fault status registers are overwritten each time an IRQ# is generated ...
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... Table 1. Fault Status register bit allocation WATCHDOG AND LONGDOG TIMERS The SMT4004A’s internal timer triggers the activation of the LDO# and WDO# outputs. LDO# and WDO# are active-low open-drain outputs that can be wire- ORed with other open-drain signals. During a power-on sequence the timers are disabled until all four Resets are released ...
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... SEQUENCE ENABLE LOGIC #2 All Resistors are 100K Ω #3 POW ER SUPPLY ARBITRATION # Figure 7. SMT4004A Internal Block Diagram. 2072 1.1 3/7/03 SMT4004A VDD_CAP RESET INTERRUPT CONTROL & FAULT STATUS REGISTERS CHARGE PUM P & VGATE CONTROL TIM ER LOGIC SERIAL INTERFACE & ...
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... SCR. The sources for initiating the pulse are user selectable and are illustrated in Figure EVD output, the pin is held high until the SMT4004A begins tracking, allowing an external MOSFET to discharge any residual voltages on the card-side power rails. ...
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... VGATE outputs are immediately turned off and clamped to ground. The FORCE_SD input is internally tied to VDD_CAP with a 100KΩ resistor. VGG_CAP is a charge storage connection for the SMT4004A internal charge pump. A 1µF capacitor rated above 16V is recommended for most applications. ...
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... Description PWR_ON is an input with a programmable active true state. It must be true for the SMT4004A to begin turning on the VGATE outputs. The PWR_ON input is internally tied to VDD_CAP with a 100KΩ resistor. Once the power- on operation is complete, de-asserting the PWR_ON input forces the tracked channels to track down ...
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... Notes: 1/ For reliable operation the VDD_CAP node voltage must ° C RELIABILITY CHARACTERISTICS Data Retention ............................................ 100 Years Endurance .......................................... 100,000 Cycles Note: Accuracy data is stored in pages 13-15 of the EEPROM memory array. Erasure of this data will render the SMT4004A GUI unusable. Loss of this data will not alter preset UV/OV trip points. 2072 1.1 3/7/03 SMT4004A 36 CB2 35 ...
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... UV1. To obtain this accuracy set to the minimum setting (decimal value = 0) and adjusted with the UV setting to reach the desired 1% OV trip point. Accuracy data is stored in pages 13-15 of the EEPROM memory array. Erasure of this data will render the SMT4004A GUI unusable. Loss of this data will not alter preset UV/OV trip points. Summit Microelectronics, Inc Conditions Min ...
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... I is the sum of all VGATE output currents. VGATE 5/ The SMT4004A adjusts the VGATE outputs to control the differential of the VOX outputs to within 100mV nominally. External influences may increase the differential until the VGATE outputs adjust to minimize the differential. 6/ Guaranteed by Design. Summit Microelectronics, Inc ...
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... PLDTO t = 1600ms PLDTO t = 3200ms PLDTO t = 6400ms PLDTO t = 25ms PRTO t = 50ms PRTO t = 100ms PRTO t = 200ms PRTO SCR Mode, R =10kΩ LOAD VGG_CAP=14V 2072 1.1 3/7/03 SMT4004A Min. Typ. Max. Unit µ µs 80 100 140 µs 160 200 280 µs -25 t +25 % PWDTO -25 t ...
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... SCL low to valid SDA (cycle n) SCL low (cycle n+1) to SDA change Note 1/ Note 1/ Noise suppression t t HIGH t LOW HD:DAT SU:DAT HD:SDA Figure 8 . Basic I C Serial Interface Timing 2072 1.1 3/7/03 SMT4004A Min Typ Max 0 100 4.7 4.0 4.7 4.7 4.0 4.7 0.2 3.5 0.2 1000 300 250 0 100 (For W rite O peration Only) t ...
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... Com posite RST DTO PW DTO W DO# t PLDTO LDO# W LDI Figure 10. Relation of LDO# and WDO# with WLDI, RST# and MR# Summit Microelectronics, Inc PWDTO t t PLDTO PLDTO <t PWDTO 2072 1.1 3/7/03 SMT4004A PRTO PRTO <t t PLDTO PRTO 17 ...
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... VGATE3 VGATE4 VO2 VO3 VO4 Com posite VO2,3 & 4 RST#s HEALTHY# Figure 11 – Timing of Events During Power-On and Power-Off sequences. Summit Microelectronics, Inc VOT P 3 VIT + P 4 VIT = P 2 VOT P 3 VOT P 4 VOT VO2 VO3 VO4 t PRTO 2072 1.1 3/7/03 SMT4004A 18 ...
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... APPLICATIONS INFORMATION Summit Microelectronics, Inc (CONTINUED) Figure 12A – Power-On Sequence of Events 2072 1.1 3/7/03 SMT4004A 19 ...
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... VGATE2 VO4&VO3&VO2 = 0V? YES IS ENABLE DEASSERTED? YES GO TO ENABLE REMOVED ROUTINE Figure 12B – Power-Off Sequence of Events 2072 1.1 3/7/03 SMT4004A ENABLE REMOVED ROUTINE SHUTDOWN ALL ACTIVE VGATE OUTPUTS IF ON DE-ASSERT HEALTHY# & OFF ASSERT ALL RST# OUTPUTS SEATED# REMOVED ROUTINE SHUTDOWN ALL ACTIVE VGATE ...
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... This allows ‘early-power’ applied to the SMT4004A so it can begin to monitor bus side supplies as they come up, and also a method to indicate the application board is fully seated and ready for operation. Removal of a ...
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... IRQ#, and if IRQ trigger source for force shutdown (FSD), the user has several options as to how the part reacts to an OV. Different options can be chosen for how the SMT4004A will respond during the time periods during power-on, after power- on has completed, or when normal monitoring is underway ...
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... If the charge is excessive (>V will not start. The SMT4004A has two options that can be selected to accommodate this situation. 1. The “Don’t-Wait-For-Zero” (DWFZ) option can be enabled ...
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... MAX applications circuits and descriptions for a system level description. RESET OPERATION Once power is applied to the SMT4004A the four The RST# outputs are driven low. meant to be used by the application circuitry, the RST# outputs remain low until all Reset trigger sources (for any manager’ ...
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... If the fault latch feature is enabled the fault condition is captured. The fault sources are a forced shutdown, CROWBAR, or IRQ#. When a fault is detected a volatile latch is set to keep the SMT4004A from being powered-up again until IRQ_CLR# is toggled. Summit Microelectronics, Inc (CONTINUED) The CROWBAR pin is designed to deliver an active high pulse to an external SCR to shutdown the card- seconds ...
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... Refer to Figures 17 and 19 for an illustration of the read sequence. MR# AND THE SERIAL INTERFACE When writing the memory array the MR# input must be high. When writing the memory array the SMT4004A cannot be in reset. When reading the status registers or memory array the state of the MR# input is ignored. ...
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... Figure 18. Write Configuration Register Sequence Configuration R Register T Address 2072 1.1 3/7/03 SMT4004A ...
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... For prototyping and device evaluation use the Windows Graphical User Interface SMX3200 device programmer with the SMT4004A. The programming system is available from the Summit website (www.summitmicro.com). Further explanation of the 32 individual configuration registers and associated GUI settings are included in Application Note 22. ...
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... RS/CB traces should be nearly of equal length and the sense resistor(s) should be as close to the SMT4004A as possible. POWER MOSFETS Selection of MOSFET switches for the SMT4004A Tracker is a compromise between load regulation, board area, and MOSFET cost. To obtain good load regulation with low supply voltages the MOSFET must ...
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... V R (BR)DSS DS(ON) 30V 2.8mΩ max. 40V 20V 3.8mΩ max. 30V 30V 4.5mΩ max. 30V 5.5mΩ max. 30V 2.8mΩ max. 30V 30V 40V 5.5mΩ max. 2072 1.1 3/7/03 SMT4004A Ω 10nF Ω T4004A VOUT to Application Circuit 5x 220µF ...
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... VO2 VGATE2 CB2 VI2 VO1 VGATE1 CB1 VI1 TM Figure 23 – IBM PowerNP NP4GS3 Network Processor Reference Platform. (Not all connections are shown. Summit Microelectronics, Inc VO4 VGATE4 CB4 VGATE3 CB3 TM Please contact IBM for further information) . 2072 1.1 3/7/03 SMT4004A VI4 VO3 VI3 31 ...
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... UV OVERIDE 3 CROWBAR C2 CROWBAR A0,A1,A2 have internal 100k pullups Figure 24 – Minimum External Component Requirements for an SMT4004A Application. See application notes 20 and 25 for additional recommendations for operation in telecom systems or noisy environments. Summit Microelectronics, Inc MOSFET N Q4 MOSFET N Q3 MOSFET N Q2 MOSFET N Q1 ...
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... SMX3200 interface cable connector. Pin 10, Reserved 0 SDA 2 1 SCL 2 C Serial Bus Connections to Program the SMT4004A. 2072 1.1 3/7/03 SMT4004A The devices are Pin 9, 5V Pin 8, Reserved Pin 7, 10V Pin 6, MR# Pin 5, Reserved Pin 4, SDA Pin 3, GND Pin 2, SCL Pin 1, GND 33 ...
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... C0 Note 1/ - Bits D5, D6 and D7 are reserved bits; therefore the contents of R18 may not be 00 The default device ordering number is SMT4004AF-181, is programmed as described above and tested over the commercial temperature range. Application Note 22 contains a complete description of the default settings and each of the 32 individual Configuration Registers. The default configuration does not include Registers R16 and R17 (virtual addresses) or R1D, R1E and R1F (Fault Status Registers) ...
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... BSC 0.276 BSC (B) (7.00) Pin 1 Indicator A Summit Microelectronics, Inc 48 PIN TQ FP PACKAGE (A) (B) (A) Ref Jedec M S-026 0.037 - 0.041 0.95 - 1.05 0.047 MAX. (1.2) B 2072 1.1 3/7/03 SMT4004A Inches (Millimeters) 0.02 BSC (0.5) 0.007 - 0.011 (0.17 - 0.27) DETAIL "A" 0.039 (1.00 Min Max 0.002 - 0.006 (0.05-0.15) 0.018 - 0.030 (0.45 - 0.75) DETAIL "B" ...
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... Date Code (YYWW) Lot tracking code (Summit use) Part Number suffix (Contains Customer specific ordering requirements) Product Tracking Code (Summit use) SMT4004A F nnn Part Number Suffix (see page 34) Specific requirements are contained in the suffix Package such as Commercial or Industrial Temp Range, F=48 Lead TQFP Hex code, Hex code revision, etc ...