AT93C46E ATMEL Corporation, AT93C46E Datasheet - Page 6
AT93C46E
Manufacturer Part Number
AT93C46E
Description
Three-wire Serial EEPROM
Manufacturer
ATMEL Corporation
Datasheet
1.AT93C46E.pdf
(15 pages)
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Timing Diagrams
Figure 2. Synchronous Data Timing
Note:
6
1. This is the minimum SK period.
AT93C46E [Preliminary]
status of the part if CS is brought high after being kept low for a minimum of 250 ns (t
The WRAL instruction is valid only at V
ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the
Erase/Write Disable (EWDS) instruction disables all programming modes and should be
executed after all programming operations. The operation of the Read instruction is
independent of both the EWEN and EWDS instructions and can be executed at any
time.
Table 6. Organization Key for Timing Diagrams
I/O
A
D
N
N
µ s
(1)
CC
= 5.0V ± 10%.
AT93C46E
x 16
D
A
15
5
5207A–SEEPR–1/07
CS
).