MT55L128L18P1 Micron Semiconductor Products, Inc., MT55L128L18P1 Datasheet - Page 5

• Manufacturer Part Number: MT55L128L18P1
• Description: 2Mb ZBT SRAM, 3.3V Vdd, 3.3V I/O, Pipelined,
• Manufacturer: Micron Semiconductor Products, Inc.

NOT RECOMENDED FOR NEW DESIGNS
PIN DESCRIPTIONS
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM
MT55L128L18P1_C.p65 – Rev. C, Pub. 11/02
80–82, 99, 100
32–35, 44–49,
TQFP (x18)
37
36
93
94
89
98
92
97
86
85
87
64
–
–
TQFP (x32/x36)
81, 82, 99, 100
32–35, 44–49,
37
36
93
94
95
96
89
98
92
97
86
85
87
64
ADV/LD#
SYMBOL
BWb#
BWd#
BWa#
BWc#
CKE#
CE2#
(G#)
OE#
SA0
SA1
CLK
CE#
CE2
S A
ZZ
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
TYPE
5
Synchronous Address Inputs: These inputs are
registered and must meet the setup and hold times
around the rising edge of CLK. Pins 50, 83, and 84 are
reserved as address bits for the higher-density 4Mb,
8Mb, and 16Mb ZBT SRAMs, respectively. SA0 and SA1
are the two least significant bits (LSB) of the address field
and set the internal burst counter if burst is desired.
Synchronous Byte Write Enables: These active LOW
inputs allow individual bytes to be written when a
WRITE cycle is active and must meet the setup and hold
times around the rising edge of CLK. BWs are associated
with addresses and apply to subsequent data. BYTE
WRITEs need to be asserted on the same cycle as the
address. BWa# controls DQa pins; BWb# controls DQb
pins; BWc# controls DQc pins; BWd# controls DQd pins.
Clock: This signal registers the address, data, chip
enables, byte write enables and burst control inputs on
its rising edge. All synchronous inputs must meet setup
and hold times around the clock’s rising edge.
Synchronous Chip Enable: This active LOW input is used
to enable the device and is sampled only when a new
external address is loaded (ADV/LD# LOW).
Synchronous Chip Enable: This active LOW input is used
to enable the device and is sampled only when a new
external address is loaded (ADV/LD# LOW). This input
can be used for memory depth expansion.
Synchronous Chip Enable: This active HIGH input is used
to enable the device and is sampled only when a new
external address is loaded (ADV/LD# LOW). This input
can be used for memory depth expansion.
Output Enable: This active LOW, asynchronous input
enables the data I/O output drivers. G# is the JEDEC-
standard term for OE#.
Synchronous Address Advance/Load: When HIGH, this
input is used to advance the internal burst counter,
controlling burst access after the external address is
loaded. When ADV/LD# is HIGH, R/W# is ignored. A LOW
on ADV/LD# clocks a new address at the CLK rising edge.
Synchronous Clock Enable: This active LOW input
permits CLK to propagate throughout the device. When
CKE# is HIGH, the device ignores the CLK input and
effectively internally extends the previous CLK cycle. This
input must meet setup and hold times around the rising
edge of CLK.
Snooze Enable: This active HIGH, asynchronous input
causes the device to enter a low-power standby mode in
which all data in the memory array is retained. When ZZ
is active, all other inputs are ignored.
3.3V I/O, PIPELINED ZBT SRAM
2Mb: 128K x 18, 64K x 32/36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DESCRIPTION
©2002, Micron Technology, Inc.