MT58L128L18P Micron Semiconductor Products, Inc., MT58L128L18P Datasheet
MT58L128L18P
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MT58L128L18P Summary of contents
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... Operating Temperature Range Commercial (0°C to +70°C) Part Number Example: MT58L128L18PT-10 2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM MT58L128L18P_C.p65 – Rev. C, Pub. 11/02 PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 2Mb: 128K x 18, 64K x 32/36 PIPELINED, SCD SYNCBURST SRAM ™ ...
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... CE2# OE# NOTE: Functional block diagrams illustrate simplified device operation. See truth table, pin descriptions, and timing diagrams for detailed information. 2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM MT58L128L18P_C.p65 – Rev. C, Pub. 11/02 PIPELINED, SCD SYNCBURST SRAM FUNCTIONAL BLOCK DIAGRAM 128K ...
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... Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version. 2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM MT58L128L18P_C.p65 – Rev. C, Pub. 11/02 2Mb: 128K x 18, 64K x 32/36 PIPELINED, SCD SYNCBURST SRAM deselected after a READ cycle, the output bus goes to a High-Z state of clock ...
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... Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version. 2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM MT58L128L18P_C.p65 – Rev. C, Pub. 11/02 PIPELINED, SCD SYNCBURST SRAM PIN ASSIGNMENT (Top View) 100-Pin TQFP ...
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... ADV ADSP# 2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM MT58L128L18P_C.p65 – Rev. C, Pub. 11/02 PIPELINED, SCD SYNCBURST SRAM TYPE SA0 Input Synchronous Address Inputs: These inputs are registered and must SA1 meet the setup and hold times around the rising edge of CLK. ...
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... NC/SA 2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM MT58L128L18P_C.p65 – Rev. C, Pub. 11/02 PIPELINED, SCD SYNCBURST SRAM TYPE Input Synchronous Address Status Controller: This active LOW input interrupts any ongoing burst, causing a new external address to be registered. A READ or WRITE is performed using the new address if CE# is LOW ...
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... WRITE All Bytes WRITE All Bytes NOTE: Using BWE# and BWa# through BWd#, any one or more bytes may be written. 2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM MT58L128L18P_C.p65 – Rev. C, Pub. 11/02 2Mb: 128K x 18, 64K x 32/36 PIPELINED, SCD SYNCBURST SRAM X...X01 X...X10 X ...
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... ADSP# LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE# LOW or GW# LOW for the subsequent L-H edge of CLK. Refer to WRITE timing diagram for clarification. 2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM MT58L128L18P_C.p65 – Rev. C, Pub. 11/02 PIPELINED, SCD SYNCBURST SRAM ZZ USED ...
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... V Q should never exceed V DD 2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM MT58L128L18P_C.p65 – Rev. C, Pub. 11/02 PIPELINED, SCD SYNCBURST SRAM *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional ...
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... than the shown DC values. AC I/O curves are available upon request should never exceed V DD 2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM MT58L128L18P_C.p65 – Rev. C, Pub. 11/02 PIPELINED, SCD SYNCBURST SRAM Q = +2.5V +0.4V/-0.125V unless otherwise noted) DD CONDITIONS SYMBOL Data bus (DQx) V Inputs 0V ≤ ...
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... Typical values are measured at 3.3V, 25°C and 10ns cycle time. 5. This parameter is sampled. 2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM MT58L128L18P_C.p65 – Rev. C, Pub. 11/02 PIPELINED, SCD SYNCBURST SRAM = +3.3V +0.3V/-0.165V unless otherwise noted) CONDITIONS SYM ...
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... Thermal Resistance (Junction to Top of Case) NOTE: 1. Typical values are measured at 3.3V, 25°C and 10ns cycle time. 2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM MT58L128L18P_C.p65 – Rev. C, Pub. 11/02 PIPELINED, SCD SYNCBURST SRAM CONDITIONS and procedures for measuring thermal impedance, per EIA/JESD51. ...
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... Chip enable must be valid at each rising edge of CLK when either ADSP# or ADSC# is LOW to remain enabled. 2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM MT58L128L18P_C.p65 – Rev. C, Pub. 11/02 PIPELINED, SCD SYNCBURST SRAM = +3.3V +0.3V/-0.165V) ...
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... SyncBurst SRAM timing is dependent upon the capaci- tive loading on the outputs. Consult the factory for copies of I/O current versus voltage curves. 2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM MT58L128L18P_C.p65 – Rev. C, Pub. 11/02 PIPELINED, SCD SYNCBURST SRAM 2.5V I/O AC TEST CONDITIONS = (V /2.2) + 1.5V Input pulse levels ............. V ...
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... ISB2Z ALL INPUTS (except ZZ) Outputs (Q) 2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM MT58L128L18P_C.p65 – Rev. C, Pub. 11/02 2Mb: 128K x 18, 64K x 32/36 PIPELINED, SCD SYNCBURST SRAM The ZZ pin is an asynchronous, active HIGH input that causes the device to enter SNOOZE MODE. When the ZZ pin becomes a logic HIGH, I ...
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... Timing is shown assuming that the device was not enabled before entering into this sequence. OE# does not cause driven until after the following clock rising edge. 4. Outputs are disabled within one clock cycle after deselect. 2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM MT58L128L18P_C.p65 – Rev. C, Pub. 11/02 PIPELINED, SCD SYNCBURST SRAM READ TIMING t ADSS ...
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... Full-width WRITE can be initiated by GW# LOW; or GW# HIGH and BWE#, BWa# and BWb# LOW for x18 device; or GW# HIGH and BWE#, BWa#-BWd# LOW for x32 and x36 devices. 2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM MT58L128L18P_C.p65 – Rev. C, Pub. 11/02 PIPELINED, SCD SYNCBURST SRAM WRITE TIMING ...
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... The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC# or ADV# cycle is performed. 4. GW# is HIGH. 5. Back-to-back READs may be controlled by either ADSP# or ADSC#. 2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM MT58L128L18P_C.p65 – Rev. C, Pub. 11/02 PIPELINED, SCD SYNCBURST SRAM READ/WRITE TIMING A3 ...
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... E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, SyncBurst, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc. 2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM MT58L128L18P_C.p65 – Rev. C, Pub. 11/02 PIPELINED, SCD SYNCBURST SRAM 100-PIN PLASTIC TQFP (JEDEC LQFP) 0.625 14.00 ± ...
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... Changed heading on Mechanical Drawing from BGA to FBGA Added 165-Pin FBGA package, REV 3/00, FINAL ..................................................................................... March/3/00 Added PRELIMINARY PACKAGE DATA to diagram 2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM MT58L128L18P_C.p65 – Rev. C, Pub. 11/02 2Mb: 128K x 18, 64K x 32/36 PIPELINED, SCD SYNCBURST SRAM 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. ...