MT58L128L32P1 Micron Semiconductor Products, Inc., MT58L128L32P1 Datasheet - Page 7

• Manufacturer Part Number: MT58L128L32P1
• Description: 4Mb Syncburst SRAM, 3.3V Vdd, 3.3V or 2.5V I/O, Pipelined, Scd,
• Manufacturer: Micron Semiconductor Products, Inc.

TQFP PIN DESCRIPTIONS (continued)
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
51–53, 56, 57,
62, 63, 68, 69, 56–59, 62, 63
13, 18, 19, 22, 72–75, 78, 79
14, 15, 41, 65, 14, 15, 41, 65,
26, 40, 55, 60, 26, 40, 55, 60,
66, 75, 78, 79,
54, 61, 70, 77 54, 61, 70, 77
67, 71, 76, 90 67, 71, 76, 90
4, 11, 20, 27, 4, 11, 20, 27,
5, 10, 17, 21, 5, 10, 17, 21,
1–3, 6, 7, 16,
(b)
25, 28–30,
(a)
72, 73
38, 39
42, 43
95, 96
8, 9, 12,
x18
58, 59,
85
31
64
23
74
24
91
–
–
22–25, 28, 29
(c)
(d)
(a)
(b)
x32/x36
12, 13
38, 39
16, 66
42, 43
2, 3, 6-9,
52, 53,
18, 19,
68, 69
85
31
64
51
80
30
91
1
NC/DQPb
NC/DQPd
SYMBOL TYPE
NC/DQPa
NC/DQPc
ADSC#
MODE
V
DNU
DQa
DQb
DQd
DQc
V
V
NC
NF
ZZ
DD
DD
SS
Q
Output “b” is DQb pins. For the x32 and x36 versions, Byte “a” is DQa
Supply Power Supply: See DC Electrical Characteristics and Operating
Supply Isolated Output Buffer Supply: See DC Electrical Characteristics
Supply Ground: GND.
Input/ SRAM Data I/Os: For the x18 version, Byte “a” is DQa pins; Byte
Input Synchronous Address Status Controller: This active LOW input
Input Mode: This input selects the burst sequence. A LOW on this pin
Input Snooze Enable: This active HIGH, asynchronous input causes the
NC/
I/O
–
–
–
interrupts any ongoing burst, causing a new external address to
be registered. A READ or WRITE is performed using the new
address if CE# is LOW. ADSC# is also used to place the chip into
power-down state when CE# is HIGH.
selects “linear burst.” NC or HIGH on this pin selects “interleaved
burst.” Do not alter input state while device is operating.
device to enter a low-power standby mode in which all data in
the memory array is retained. When ZZ is active, all other inputs
are ignored.
pins; Byte “b” is DQb pins; Byte “c” is DQc pins; Byte “d” is
DQd pins. Input data must meet setup and hold times around
the rising edge of CLK.
No Connect/Parity Data I/Os: On the x32 version, these pins are
No Connect (NC). On the x18 version, Byte “a” parity is DQPa;
Byte “b” parity is DQPb. On the x36 version, Byte “a” parity is
DQPa; Byte “b” parity is DQPb; Byte “c” parity is DQPc; Byte “d”
parity is DQPd.
Conditions for range.
and Operating Conditions for range.
Do Not Use: These signals may either be unconnected or wired to
GND to improve package heat dissipation.
No Connect: These signals are not internally connected and
may be connected to ground to improve package heat
No Function: These pins are internally connected to the die and
have the capacitance of input pins. It is allowable to leave these
pins unconnected or driven by signals. Reserved for address
expansion; pin 43 becomes an SA at 8Mb density and pin 42
becomes an SA at 16Mb density.
dissipation.
7
PIPELINED, SCD SYNCBURST SRAM
4Mb: 256K x 18, 128K x 32/36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DESCRIPTION
©2003, Micron Technology, Inc.