MT90210 Zarlink Semiconductor, MT90210 Datasheet - Page 7

• Manufacturer Part Number: MT90210
• Description: 3072 Channels TDM to Dual Port RAM Multiple Rate Parallel Bus Access Circuit (MRPAC)
• Manufacturer: Zarlink Semiconductor

MT90210
how the data from the serial port is mapped into the
external dual port memory.
Mode 2 : When the device is configured for
4.096 Mb/s data rate operation, each of the 24 time-
division multiplexed serial streams is made up of 64
channels. In this data rate operation, the 24 serial
lines
4.096 Mb/s. Serial port clock (SCLK) is 8.192 MHz.
The on-chip PLL produces a phase locked 32.768
MHz clock (CKout) from the SCLK input. Figure 4
depicts how the data from the serial port is mapped
into the external dual port memory.
Mode 3 : When the device is configured for 8.192
Mb/s data rate operation, each of the 24 time-
division multiplexed serial streams is made up of 128
channels. In this mode, bidirectional operation on the
serial port streams is not provided and the MT90210
is set in a 12 in / 12 out configuration and the OEser
input is ignored. Streams S0-S11 are configured as
inputs, and S12-S23 are configured as outputs.
Serial port clock is 16.384 MHz. The on-chip PLL
doubles this clock to produce a CKout clock of
32.768 MHz. Figure 4 depicts how the data from the
serial port is mapped into the external dual port
memory. Figure 12 and Table 3 show the write and
read operations on the parallel port at the frame
boundary.
2-150
Figure 3 - Dual Port RAM Memory Map for
(S0-23)
BLOCK 0
BLOCK 1
24 bidirectional streams at 2.048Mb/s
Address outputs used: A0-A11;
A12 always zero.
Legend:
unused memory space
become
768 bytes
768 bytes
768 bytes
768 bytes
Mode 1
MODE 1
for RX
for RX
for TX
for TX
bidirectional
0AFF
0C00
0EFF
0FFF
0000
02FF
0400
06FF
0800
links
at
Mode 4: The MT90210 is configured such that the 24
serial streams are bidirectional and split into two
different functional groups: (i) streams S0-S15
operate at 2 Mb/s rate (512 timeslots), (ii) S16-S23
operate at 8.192 Mb/s rate (1024 timeslots). Memory
mapping for mode 4 is described in Figure 5. For
compatibility with legacy MVIP timing, mode 4
provides an additional clock input at 4.096 MHz
(HC4 input pin) which allows the device to detect
frame sync pulse (F0i) with a typical width of 244 ns.
In mode 4, the 16.384 (SCLK) and 4.096 (HC4) MHz
clocks should be in sync according to H-MVIP
specifications. The on-chip PLL doubles SCLK to
produce a CKout signal of 32.768 MHz. Figure 13
and Table 4 show the write and read operations on
the parallel port at the frame boundary.
Mode 5 : Identical operation as per mode 4 with the
difference that the 16.384 MHz clock is a differential
signal received at the two input pins, C16+ and C16-
of the MT90210 device. The differential clock is
needed to eliminate distortion in the clock signal
passing through a ribbon cable as per H-MVIP
specification. The SCLK input is not used in this
mode. Memory mapping for mode 5 is depicted in
Figure 5.
Figure 4 - Dual Port RAM Memory Map for
BLOCK 0
BLOCK 1
24 bidirectional streams at 4.096Mb/s,
or 12 in / 12 out at 8.192Mb/s
Address outputs used: A0-A12
Legend:
unused memory space
MODES 2 & 3
1536 bytes
1536 bytes
1536 bytes
1536 bytes
for RX
for RX
for TX
for TX
Modes 2 and 3
0DFF
1DFF
1FFF
0000
05FF
0800
1000
15FF
1800