MT90222AG Zarlink Semiconductor, MT90222AG Datasheet - Page 99

• Manufacturer Part Number: MT90222AG
• Description: Description = 4 Port Ima & TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
• Manufacturer: Zarlink Semiconductor

Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
15:12
Bit #
Bit #
11:8
15:9
7:4
3:0
8:5
3:0
4
Type
Type
R/W
R/W
R/W
R/W
R/W
R
R
R
Unused. Read all 0’s.
Defines the integration period for an IMA Group n+4
1111: Reserved. Do not use.
1110: 2
1101: 2
...
0001: 2
0000: 2
Reserved. Write all 0’s.
Defines the integration period for an IMA Group N
1111: Reserved. Do not use.
1110: 2
1101: 2
1100: 2
1011: 2
1010: 2
1001: 2
1000: 2
0111: 2
0110: 2
0101: 2
0100: 2
0011: 2
0010: 2
0001: 2
0000: 2
Unused. Read 0.
Reserved. Value may
When set to 1, it enables the automatic selection of the Reference link for the Group N.
When 0, the link specified in bits 3-0 is used as the reference link.
These 4 bits specify which physical link is to be used as the reference link for the IMA
Group N.
0x0219 - 0x021C (4 reg)
1 register per 2 IMA groups. IMA Group 0 is paired with IMA group 4 and so on.
For MT90222 only groups 0,1,2 and 3 are used.
0C0C
0x0209 - 0x0210 (8 reg)
0000
1 register per IMA Group. For MT90222 only groups 0,1,2 and 3 are used.
22
22
15
21
21
20
19
14
11
09
08
18
17
16
13
12
10
09
08
Table 57 - RX Reference Link Control Registers
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles (preferred value for E1 with 30 channels)
clock cycles (preferred value for T1 with 24 channels)
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles (preferred value for T1 ISDN with 23 channels)
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
Table 58 - RX IDCR Integration Registers
vary.
Zarlink Semiconductor Inc.
MT90222/3/4
99
Description
Description
Data Sheet