MT90225AG Zarlink Semiconductor, MT90225AG Datasheet - Page 54
MT90225AG
Manufacturer Part Number
MT90225AG
Description
Description = 16 Port TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
Manufacturer
Zarlink Semiconductor
Datasheet
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Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Synchronized access
Reset Value (Hex):
15:12
Bit #
Bit #
15:4
9:8
1:0
11
10
3
2
1
0
7
6
5
4
3
2
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Unused. Read all 0’s.
Set when the UTOPIA output clock is missing or too slow. This latched bit is cleared by
writing a 0.
Set when the UTOPIA input clock is missing or too slow. This latched bit is cleared by
writing a 0.
Overflow of 1 or more of the TX UTOPIA FIFO.
Set when there is no free cell in TX Cell RAM. This latched bit is cleared by writing a 0.
Unused. Read all 0’s.
Reserved. Write 0 for normal operation.
Counter values are latched when this bit is changed from 0 to 1 and bit 9:8 are set to 11.
Writing 0 has no effect.
Write 00 for normal operation without using the latch made.
Write 01 to latch the counter value at every rising edge of the signal at LatchClk pin.
Write 10 to latch the counter value every 8000 rising edges of the signal at LatchClk pin.
Write 11 to latch the counter value every time bit 10 of this register is written to 1.
Write: 0 for normal operation.
Read: 1 when the transfer is done, 0 when the transfer is pending.
Toggle bit. Toggles with every write access to MT90225/226. Write 0 for normal
operation.
Reserved. Write 0 for normal operation. Read value is undetermined.
Reserved. Write 0 for normal operation.
Value to write to the Enable bit. 1 to enable, 0 to mask interrupt. This value is transferred
when the bit 1:0 are 10.
0 will enable the transfer from the uP to the selected counter.
1 will enable the transfer from the selected counter to the uP.
00: Initialize all the counters with 0.
01: Initiate a read or write of the counter value.
10: Initiate a read or write of the IRQ enable counter bit.
11: Unused.
0x040E (1 reg)
0000
0x040F (1 reg)
0080
Table 23 - Counter Transfer Command Register
Table 22 - General Status Register
Zarlink Semiconductor Inc.
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