MT9160B Zarlink Semiconductor, MT9160B Datasheet - Page 6

• Manufacturer Part Number: MT9160B
• Manufacturer: Zarlink Semiconductor

MT9160B/61B
Motorola/National operation. Refer to the relative
timing diagrams of Figures 5 and 6.
Receive data is sampled on the rising edge of SCLK
while transmit data is made available concurrent with
the falling edge of SCLK.
84
DATA 1
RECEIVE
DATA 1
TRANSMIT
SCLK
CS
DATA 2
RECEIVE
DATA 1
TRANSMIT
SCLK
CS
subsequent byte is always data until terminated via CS returning high.
subsequent byte is always data until terminated via CS returning high.
The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The
The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The
Delays due to internal processor timing which are transparent.
The MT9160:-latches received data on the rising edge of SCLK.
A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.
The COMMAND/ADDRESS byte contains:
Delays due to internal processor timing which are transparent.
A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.
The COMMAND/ADDRESS byte contains:
The MT9160:-latches received data on the rising edge of SCLK.
D
D
7
0
D
D
Figure 5 - Serial Port Relative Timing for Motorola Mode 00/National Microwire
-outputs transmit data on the falling edge of SCLK.
-outputs transmit data on the falling edge of SCLK.
COMMAND/ADDRESS
6
COMMAND/ADDRESS
1
D
D
5
2
D
D
4
3
D
D
3
4
Figure 4 - Serial Port Relative Timing for Intel Mode 0
D
D
2
5
D
D
1
6
D
D
0
7
1 bit - Read/Write
3 bits - Addressing Data
4 bits - Unused
1 bit - Read/Write
3 bits - Addressing Data
4 bits - Unused
D
D
D
D
0
7
7
0
D
D
D
D
1
6
6
1
DATA INPUT/OUTPUT
DATA INPUT/OUTPUT
D
D
D
D
2
5
5
2
D
D
D
D
4
3
3
4
D
D
D
Flexible Digital Interface
A serial link is required to transport data between the
MT9160B/61B and an external digital transmission
device. The MT9160B/61B utilizes the ST-BUS
architecture defined by Zarlink Semiconductor but
D
3
4
4
3
D
D
D
D
2
5
5
2
D
D
D
D
1
6
6
1
D
R/W
X
7
D
D
D
D
D
7
0
7
7
0
X
X
D
D
D
D
7
0
7
0
X
X
D
D
D
D
6
1
6
1
COMMAND/ADDRESS:
COMMAND/ADDRESS:
Advance Information
D
D
D
D
X
5
X
2
2
5
D
D
D
D
3
4
3
A
4
A
2
D
D
2
D
D
4
3
4
3
D
D
A
D
D
A
1
5
2
5
2
1
D
D
D
D
6
1
6
1
A
A
0
D
D
D
D
0
7
0
0
7
R/W
D
D
X
0
0